Big SMPS Help!

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M

mgm2000ro

Member
Joined 2004
Hello and thank you for the input!
I have taken some detailed pictures which I hope will help with debugging.
If it's needed I can remove the PNP transistor and use R+D and protection zenners.

waveform U g-e IGBT idle smps:
http://img812.imageshack.us/img812/3218/150120121156.jpg
ZOOM
http://img51.imageshack.us/img51/6130/150120121159.jpg

waveform yellow U g-e IGBT idle smps
waveform blue U c-e IGBT idle smps
http://img843.imageshack.us/img843/3856/150120121161.jpg
ZOOM blue waveform invert !
http://img850.imageshack.us/img850/5749/150120121164.jpg


waveform yellow U g-e IGBT, smps 50A loud 14.4V
waveform blue U c-e IGBT, smps 50A loud 14.4V (waveform invert)
http://img94.imageshack.us/img94/4210/150120121165.jpg
Zoom turn-on
http://img269.imageshack.us/img269/9923/150120121166.jpg
Zoom turn-off
http://img94.imageshack.us/img94/8877/150120121167.jpg

It is necessary to eliminate pnp?
 
C

ChocoHolic

Member
Joined 2003
The shapes are not looking bad.
The only strange thing is that Uge gets smaller at higher duty cycles.
If this trend goes on with increasing duty cycle, you may run the switches in linear mode at heavier loads....
For me you do not need to remove the pnp or zeners.
I would be more interested in seeing the gate drive at high duty cycles. As described earlier the simplest method is to do this with a 15-30V lab supply to feed the upper collector, no load or light load.
 
M

mgm2000ro

Member
Joined 2004
D

DjLeco

Member
Joined 2006
As I can see, no deadtime there.

A minimum 100-350 nSecs must be as deadtime to avoid overshoot (crossconduction).

Use as I said, or specilalised IGBT driver or separate trafo's, for each IGBT to obtain some deadtime between high and low side (adjustable from PWM circuit).

Crossconduction is 90% guilty for smps or class d failure, excluding undersized components or bad pcb layout..
 
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M

mgm2000ro

Member
Joined 2004
Hello Leco, I am anxious to see the pictures of your super-power supply(or an video :) )
Speaking of dead-time, are you 100% sure that there is any in this picture ? Because I am very confused.
What does this hole represent ?
U c-e and U e-c (gnd-oscilloscope is on E of high-side IGBT and on C of low-side IGBT )
An externally hosted image should be here but it was not working when we last tested it.

Best regards!
 
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C

ChocoHolic

Member
Joined 2003
@mgm:
I am also wondering why DJ says there would be no dead time.

Still the only thing which is looking critical to me is the gate drive level in this picture.
http://img94.imageshack.us/img94/4210/150120121165.jpg
It shows approx. 7V Uge, which is already at the lower end of acceptable levels.
If this turns worse at higher loads you may have linear operation of the switches and excessive losses may cause failure.

In your last post you are also showing Uge at max duty cycle.
http://img205.imageshack.us/img205/949/170120121168.jpg
Here the gate drive level is fine, Uge approx 10V.
I guess you checked this without load and low rail voltage?
It seems like there is a effect that reduces your gate drive level at heavy loads.
So my next step would be to settle again the same situation with 50A load and get again the picture with low gate drive...
http://img94.imageshack.us/img94/4210/150120121165.jpg
...and then trying to understand why the gate drive level is getting lower.
12V-supply stable?
Output level of driver stable?
Output level of transformer winding stable?

Comparison of gate drive level at 30A, 50A, 70A?

Sorry for flooding you with proposals what to check.
Many readers, many proposals.
Feel free to check according your own opinion which checks will help most.

@dtproff/Toni
No opinion/proposals from your side??
Btw, thanks for your link.
 
M

mgm2000ro

Member
Joined 2004
C

ChocoHolic

Member
Joined 2003
Most likely the scope does not play tricks.
Even when considering a perfect operation, the duty cycle of the gate drive signals must vary with double line frequency.
The 310V are not constant 310V, at higher load this voltage will sag and show a heavy modulation with double line frequency. In order to keep the output voltage stable the 3525 must vary the duty cycle.

...you say very instable ...and the scope is struggling everytime to catch it....
Is only the duty cycle varying, or also the shape and/or magnitude?

Please also note:
When comparing two different screen shots at 50A:
http://img94.imageshack.us/img94/4210/150120121165.jpg
and
http://img443.imageshack.us/img443/898/180120121211.jpg
==>
We see different duty cycles and different magnitudes.
The new picture looks like beeing catched in a moment with high supply voltage, the other one in a moment at lower input voltage.

I am not aware of the detailed triggering features of your scope.
The easiest method ( and also possible with every scope) to catch the wave forms at different moments of higher or lower supply voltage, is to use chanel 1 to measure the supply voltage and chanel 2 for the lower gate signal.
Triggering on chanel 1. You can now adjust the trigger level on any relevant input voltage and will get the related gate wave shape on the chanel 2.

Up to now the shown wave forms indicate that the critical operating area might be at high current loads during moments, when the supply voltage is sagging to lower values.

Please note:
You are mostly presenting nice screen shots.
The interesting wave forms when searching reasons for defects are generally the not so nice looking screen shots.

P.S.
I am still suspecting that your 12V is sagging with the sagging of the 310V.
Schematic of this part would be nice.
Measuring the stability of the 12V under all load conditions is one of the fundamental checks anyway, even if the smps would not show defects.

P.P.S.
Pin 9: Well, your configuration is not my favorite, but most likely you got it from a working design. I would not expect that it is the reason for the defects.
In order to get a rough idea if the loop is doing something reasonable or just chaos, you can watch the voltage at pin9 with a time scale of 2ms/grid at 50A load. If you see a DC level with additional AC signal of double mains frequency, then the loop is doing something reasonable (optimization is by far more complicated). If you see additional ringing effects at pin 9 then this would indicate a tendency to instability.
 
C

ChocoHolic

Member
Joined 2003
Glad to read that you found and solved issues with the auxiliary 12V supply for the chips.
It is hard to tell from a distance whether all issues are solved now, but seeing a stable gate drive level now is promising.
The visible jumping of signals could be related just to triggering or to intermitting operation.
Intermitting operation is something you would hear as a fluctuating instable rattling noise. If it is not intermitting - promising.

If not intermitting:
Did you already dare to run at 200A for longer time?
Try to do thermal measurements (equipment available?) directly on the IGBTs during short term load. Losses which do not instantly kill the MosFets, but within seconds - usually are visible as a fast temperature increase. If temperature appears undramatic, you can dare to step up the load duration, while going on to track the temperature...

Edit:
- MosFets: I meant IGBTs....
- undramatic: With respect to the package of the IGBT, the temperature should remain almost stable if loaded just for a second.
 
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M

mgm2000ro

Member
Joined 2004
I tested the SMPS for 10 minutes 14.5V - 50A , and results are :
Temp IGBT = 55°C (beack heatsink)
Temp diodes = 58°C (beack heatsink)
Temp transformers = 43°C (on the wires)
Temp output inductor = 65°C (on the wires)
Temp resistor from snubber from each igbt = 103°C
I have a single heatsink from igbt + dioses.
http://img832.imageshack.us/img832/8281/imggdphp.jpg
efficiency = 88,4%
In:280Vdc x 2.91Adc => ~815W
Out: 14.51Vdc x 49.7Adc => 721W
It is ok?
 
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C

ChocoHolic

Member
Joined 2003
..so far nothing extraordinary. Also the fact that the diodes generate more heat than the switches, indicates that at 50A there are no switching catastrophies. But it is clear that this design cannot handle 200A continuosly, at least not without forced cooling.
Nevertheless it should not burn within some single seconds at 200A.
If the sagging auxiliary supply and sagging gate drive was the only electrical short coming and is cured now, then 200A should be possible for multiple tens of seconds without defects.

For which application would you need it? Really 200A continuously? Electrolytic etching bath?

Or HiFi? If Hifi, forget the continuos requirement. Music program does not contain continuous max level for more than a few seconds.
 
M

mgm2000ro

Member
Joined 2004
Hello all !
I return after several failures for up 130A (6 igbt and 2 mosfet blow).
Now i have eliminate PNP configuration driver and i put R+ D in Gate and G-E zenner protecta (simple configuration with positive and negative voltage)!
I put an primary winding a current transformers PPAS102 1:200 whit 390 ohm resitors
Waveform U and I of primary winding , output loud 14.4V 50A
http://img835.imageshack.us/img835/126/260120121228.jpg
 
C

ChocoHolic

Member
Joined 2003
Does not look like bad trouble.
The difficulty is to get the screen shots, which point to issues, without actually getting defects.
Did you you try to increase the load slowly and always check all wave forms?
Usually you start seeing massively growing imperfection of at least one wave form before things turn destructive.
Uge? Uce? Iprim? Uprim?

You say you get defects at 130A...
After which time do they happen at 130A?
 
D

DjLeco

Member
Joined 2006
Trying to help mine country mate, I post here some waveforms on primary SMPS trafo, and curent on it, taken by a seried resistor in primary circuit of 0,1 ohms value.

The measurement circuit was:


http://postimage.org/image/wgtxklwpn/

SMPS in idle,loaded around 45-50 watts, by a bulb of 230volts 60 watts,on 214 Vcc on secondary capacitors, Vcc being +/- 107Vdc, unregulated:

Yellow is Primary trafo smps tension, blue is primary curent , and SMPS is UNREGULAED at this tests.



http://postimage.org/image/6gtv7tneb/


SMPS , loaded at around 1700 watts, with dummy load:


http://postimage.org/image/pv2a3gj9b/


Also here is measured primary tension (yellow) and voltage (blue) across resonant capacitor in idle mode:

http://postimage.org/image/kpgmnevnh/

And here is measured primary tension (yellow) and voltage (blue) across resonant capacitor in 1700 watts load mode:

http://postimage.org/image/rjqxd3oal/

Both of us, are waiting for opinions, comments.
 
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C

ChocoHolic

Member
Joined 2003
You are showing two times the load situation with 1700W and in both screen shots you state the yellow to be the voltage across the primary of the pimary transformer.
We should expect that the voltage across the primary at 1700W looks the same on both screen shots, but it does not.
View image: DSCN5360
View image: Loa
Is it really just the different time scale, which makes it looking different or is there also a changed test set up? May be 3oal without shunt resistor?

In any case I do not see heavy catastrophies.
There seem to be two resonances.
The faster one (right at/after stepping of the primary voltage) might be triggered by the reverse recovery of the diodes on the secondary.
It is always a matter of taste and/or regulations how much efforts to spend on such effects or just live with it as long as they do not generate destructive load conditions to any component.
 
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