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Old 7th May 2011, 09:21 PM   #1
kubeek is offline kubeek  Czech Republic
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Default 750W SMPS

Here is my first smps project, so I would love to hear what can be improved on the design and PCB. It is intended for audio amps, and should be delivering about 9 amps. Core is etd44, working on 75kHz.
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Old 8th May 2011, 08:22 PM   #2
hesener is offline hesener  Germany
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the PCB traces on the secondary side look very thin.... for this current it might be better to put much wider traces.also , the rectifiers may be a little weak for these currents (if you want to operate it at full power continuously, especially)

just my two cents
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Old 8th May 2011, 09:03 PM   #3
AP2 is offline AP2  Italy
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Hi, sorry if I say something about the protection circuit.
The first part up to comparator, it makes sense, in shuntdown mode switch if the current exceeds the threshold (positive and negative sense, is correct).
circuit after the comparator does not make sense. fails to protect the short circuit is already present at switch-on psu. in practice it is redundant.
Other problem (but unfortunately not only on this scheme), is the use of feedback relating to only one side of DC. especially when the amplifier works at low frequencies, the psu create huge imbalance. this causes great imbalance on ofset of amplifier with relative high thd. Also,this system produce audible thd on percussion sound. (burst signal)
it is easier to think a good smps unregulated, with good filters. my opinion

Regards
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Old 8th May 2011, 10:53 PM   #4
kubeek is offline kubeek  Czech Republic
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Thank you for your replies.
hesener: the traces are mostly just to see the connections, when I finalize the board they will be much wider.
IŽll have to calculate the dissipation on that bridge.

AP2:The circuit after the comparator discharges the soft start capacitor on the sg3525 and holds the shutdown pin high for about 3 secs, then the softstart rans again.
I want to use bridged amplifiers with it, so the secondary voltage imbalance should not be a problem.

I also forgot to say that this will be unregulated at first, then I will start playing with possible feedback and compensation.
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Old 9th May 2011, 07:01 PM   #5
sbrads is offline sbrads  United Kingdom
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Have you got R13 and R14 in different circuit positions re layout vs. circuit diagram? I'm going boss eyed trying to work it out.

Also, can't see how the 12v supply to the output drivers IC2 and IC3 works. If it's the same supply to both then the bottom O/P FET Q2 must be shorted drain/source through the return side of +12v being on both Q1 source and Q2 source. I know you don't show AGnd on the source of Q1, but if it's not there at all then how is IC2 powered by a steady 12v DC? Apologies if I've missed something obvious.
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Old 9th May 2011, 08:05 PM   #6
kubeek is offline kubeek  Czech Republic
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Thank you sbrads, I had an error in the resistors.
The supply for IC3 is 12V against the low rail, so when Q2 turns on the mosfet midpoint is pulled low and the caps near IC2 get charged through D7. The wires are not on the board yet, probably will be through air.
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Old 10th May 2011, 12:32 PM   #7
marce is offline marce  United Kingdom
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The track width for 9A will depend on the weight of copper used to make the PCB as follows (these figures are for a 20deg C temp rise over ambient):
1oz copper (35um) 0.4" (10mm)
2oz copper (70um) 0.2" (5mm) - hard to get for home etching
I use copper pours (max copper) for any signal requirement over 6amps, this gives more surface area for heat dispersion and plenty of leeway. I would also look at adding some ground pours around high current/ high delta I switching areas for again current handling but also EMC compatibility. There is also a ground! that goes to LSP2 going through single vias, again I would use a copper area and multiple vias to reduce via resistance and inductance. Any high current/voltage switching loops should be minimised.
For creepage and clearance you'll need at least 8mm between any high voltage and low voltage areas, and best to add a warning high voltage symbol to the PCB.
Some layout observations.
Move D3, D4, D5 and D6 to minimise track length. Track from L5 going under L4 very susceptible to inductive coupled noise by running under L4. I would group the Inductors/capacitors closer together and again use copper pours again to minimise EMC and noise problems. Q1 end pin to Q2 middle pin to transformer starts of fat then changes layer to a small track on opposite side, not good, and again as they are switching they should be places as close as possible to transformer

Last edited by marce; 10th May 2011 at 12:51 PM.
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