Let's talk gate drive rise time and noise

[leadcoma]

Many of the app notes relating to gate drives are mentioning rise times of 50 to 100nS. I can achieve close to this with a totem pole bipolar drive but the fast RT generates excessive noise on the output of my half bridge SMPS.

For example, at 110nS RT and 80nS FT, the noise on my +6Vdc output before the linear regulator is about 600mVpp. This is not ripple, it's spurious noise. If I slow down the RT, the noise is reduced. At RT=500nS, it's down to 240mVpp.

At the 110nS RT, there's no ringing, the gate waveform is very clean and of course it's even cleaner with the 500nS RT. There's no shoot through, leakage inductance of the transformer is 4nH (hand wound), operating flux is 200mT using an ETD39 3F3 core.

What RTs and noise are other people measuring? I'd like to target 100nS RT and keep the MOSFETs running cooler but how to minimize the noise on the transformer output?

[leadcoma]

opps, make that 4uH leakage inductance

[infinia]

I think noise or EMI relates more directly to parasitics esp XFMR inductive leakage, and PCB layouts, component parasitics, rather than rise/fall times which tend to excite said resonances both by the primary switches and secondary (rectifiers) switches. The more parasitics the slower operating frequencies, longer dead times and tr,tf to realize lowest EMI designs. It's better to fix the parasitics best you can 1st rather to slow things down. Sorry this is only a philosophy and doesn't help your specific design. perhaps more snubbers?

[leadcoma]

Thanks for responding.

The highest amplitude switching noise on the secondary is centered around 10Mhz. The secondary rectifiers are snubbed. The ringing freq is 40Mhz, amplitude is <500mVpp.

The primary switches, exposed to a voltage of 330Vpp, are relatively clean, < 1Vpp ringing amplitude at about 4Mhz.

Of course the layout isn't perfect but I'd expect to be able to find the source of the noise by probing around. Still looking