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Old 24th January 2013, 06:02 PM   #161
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Quote:
Originally Posted by nigelwright7557 View Post
I found 390pf caused the transformer to vibrate a little.
With 1000pf it is dead quiet.
I obviously recalculated Rmin and Rmax to suit from the spread sheet.
Dont change the timing capacitor. Do the scope measurements I said and post the scope pictures if you can.
From the picture i can tell you if your dead-time is too small or too big.
So we can fine-tune your network
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Old 24th January 2013, 09:12 PM   #162
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Quote:
Originally Posted by lorylaci View Post
Dont change the timing capacitor. Do the scope measurements I said and post the scope pictures if you can.
From the picture i can tell you if your dead-time is too small or too big.
So we can fine-tune your network
I cant scope the primary as I don't haver an isolation transformer.
I can look at the secondary ok ?

1 uS per division.

Click the image to open in full size.

Last edited by nigelwright7557; 24th January 2013 at 09:33 PM.
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Old 24th January 2013, 09:52 PM   #163
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Quote:
Originally Posted by nigelwright7557 View Post
I cant scope the primary as I don't haver an isolation transformer.
I can look at the secondary ok ?
From the secondary waveform I cannot tell whether the dead-time is ok.

Gate és félhíd ÉLES.gif
Here you can see my waveforms. Green is the low side FET gate, and yellow is the half bridge output.
The gate turns on (gets over 3V) just after the half bridge has sunk to low.
When the half bridge is sunk to low, you can see a negative spike. This negative spike is just before rising.
If this is negative spike is >100ns before the gate signal starts to rise, then you have too much dead-time.

I did some simulations for you too (with IRF740, 200kHz switchin, 200uH primary inductance and 47nF resonant capacitor):
Nigel_toomuch.png
Here you can see a situation where dead-time is too much (it is set to 500ns). You can see that the negatíve spike happens about 400ns before the rise of the gate.
Nigel_justgood.png
Here you can see a situation with proper dead-time (it is set to 100ns). The negative spike is just before the gate signal rise (like me scope measurements).
See that the half bridge slope is the same with big dead-time.
Nigel_tooless.png
Here the dead time is set to very little (50ns). You can see a miller plateu-caused positive spike in the gate rising. Also note that the half bridge slop starts with a slow slope, then it changes at a ceratin point and sinks rapidly (hard swithcing, high dU/dt).

In the simulations a dead-time values of 200-100ns was found good for this situation. Usually there is no perfect dead-time value.
At no load swithcing freq is at maximum, so you must set the minimum needed dead-time. At load the switching fequency decreases and the magnetizing current gets bigger, also the leakage inductance helps you a bit, so FETs Coss charges more rapidly. At lower switching freq, a lower dead time is also enough.
Some ICs have adaptive dead-time (they change the dead-time with switching frequency).
But IRS27951 has a selectable fixed dead-time. So you must set it at no-load to the minimum needed value. It will be a bit much at high load, but no problem.
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Old 25th January 2013, 12:02 AM   #164
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I have Fmin as 27,777Hz.
I Fr1 as 66,666Hz
I have Fmax as 133,332Hz

If I run my 27951 off low volts I get 43KHz as the minimum frequency.
I get 153KHz as the maximum frequency.

Is the 43KHZ close enough to 27,777Hz ? Should it not need to be close to the lower resonant frequency as possible but not below it ?
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Old 25th January 2013, 12:20 AM   #165
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Quote:
Originally Posted by lorylaci View Post
From the secondary waveform I cannot tell whether the dead-time is ok.
.
The highest isolated voltage I could find was 90 volts and this is what I get:

The first top upmost is the half bridge out and the other signal is LO.
Its looks around 800nS dead-time.

Click the image to open in full size.
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Old 25th January 2013, 01:43 AM   #166
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I worked through the app notes again tonight.
Together with the spread sheet I tried to work out where everything was coming from.
I was getting the minimum switching frequency mixed up with the lower resonant frequency.

I also did a silly with the formulae, I used 10e-3 instead 10 power of -3 so was out by a factor of 10.

I now get the same values as the spread sheet for the control components.

Last edited by nigelwright7557; 25th January 2013 at 01:46 AM.
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Old 25th January 2013, 06:10 AM   #167
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Quote:
Originally Posted by nigelwright7557 View Post
The highest isolated voltage I could find was 90 volts
A nice tip:

If you don't have a transformer with higher voltage output, use a voltage multiplier rectifier to make the voltage higher.
You need to check the waveform at no load, so it only need to take few watts.
The circuit can be supplied with both 230VAC and 320V DC (then the rectifier brdige does nothing, but no problem
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Old 25th January 2013, 06:47 AM   #168
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Q: how do you design the transformer with the aim of a certain Lleak? . Lm is no.problem (turns, core data, air gap) but how to make sure that you end up at the right ballpark?
spilt bobbin etc .

The reason is that I was at first considering using an external inductor but then I realised that it will have quite some current swing at high frequency, sinusodial (does not matter) . This rules out a cheap nifty iron powder toroid and basically I need quite a large air gapped ferrite ( due to flux losses) i e two sets of ferrite transformers , one quite large (an ETD29 will not be able to bear the flux unless you use ridicously air gaps)
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Old 25th January 2013, 04:28 PM   #169
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Quote:
Originally Posted by rikkitikkitavi View Post
Q: how do you design the transformer with the aim of a certain Lleak? . Lm is no.problem (turns, core data, air gap) but how to make sure that you end up at the right ballpark?
spilt bobbin etc .
After winding about 5-10 SMPS transformers, you will have an expereience to get about good leakage inductance. Also +/-10% difference can be compensated by other tags (setting Lm and Cr, and then adjusting the freqs at controll).

Also there is a good approximation for split bobbin:
Calculate Al with a gap of half the winding width (9mm for ETD29, 13mm for ETD39) then Lleakage=turns^2*Al


Quote:
Originally Posted by rikkitikkitavi View Post
The reason is that I was at first considering using an external inductor but then I realised that it will have quite some current swing at high frequency, sinusodial (does not matter) . This rules out a cheap nifty iron powder toroid and basically I need quite a large air gapped ferrite ( due to flux losses) i e two sets of ferrite transformers , one quite large (an ETD29 will not be able to bear the flux unless you use ridicously air gaps)
The size of an external series inductor is usually half of the main transformer (if the transformer is wound to low leakage).
For example for my >1kW LLC converter: Lm=45uH, with a K of 5 to 8 the series inductance should be Ls=5,5 to 9 uH. My transformer had a leakage indutance of 4uH with split bobbin. So I use split bobbin (large leakage inductance) + an external small series inductance (2-4 uH) to set the correct series inductance.
This way the series inductor has a size of 1/10th of the main transformer. Its a small SMD one with flat wire. This is a good compromise method, and this way you can set both Lm and Lr very accurately. (while maintaining small size and cost)
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Old 25th January 2013, 05:27 PM   #170
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thanks. never really looked.into it before but it is probably as you say.

Using a split bobin would make it easier reaching sufficient isolation voltage assuming creepage etc is cared for. I use triple insulated wire anyhow. For a LLC operating around 100 kHz perhaps litz is a good idea considering the large circulating currents and losses.

I was thinking abot splitting Ls into Ll and Lexternal as you did in your 1 kW just after my first post.

Anyhow Lm cannot be calulated accurately unless quite large air gaps are involved sawmping.out differnces in u.
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