Hi!
I've designed a class-d amplifier using TDA8920BJ and this SMPS on the bottom of it. It is a push-pull topology and the transformer core is ETD39. Efficiency of the SMPS is about 80% and the controller circuit is SG3525.
I have one question at this point: what happens when the voltage on the battery drops so low, that the feedback cannot sustain the correct output voltage? The PWM-controller of course raises the pulse width to about 50% on both outputs but is this dangerous? The input current to the SMPS seems to stay approximately constant. I don't understand transformers very well. Why it does not input more current when the pulse width rises?
The transformer has 4+4 turns on primary and 9+9 on secondary winding. The output voltage is adjusted to about +-25V so the low-limit for input for the circuit to enter max. (50%) pulse width is about 11.1V.
I think the transistors do not enter the saturation region since the output voltage is always >8V (they should remain fully open at this point). I can post pictures too.
Any tips for improving efficiency?
And btw. very nice forum
I've designed a class-d amplifier using TDA8920BJ and this SMPS on the bottom of it. It is a push-pull topology and the transformer core is ETD39. Efficiency of the SMPS is about 80% and the controller circuit is SG3525.
I have one question at this point: what happens when the voltage on the battery drops so low, that the feedback cannot sustain the correct output voltage? The PWM-controller of course raises the pulse width to about 50% on both outputs but is this dangerous? The input current to the SMPS seems to stay approximately constant. I don't understand transformers very well. Why it does not input more current when the pulse width rises?
The transformer has 4+4 turns on primary and 9+9 on secondary winding. The output voltage is adjusted to about +-25V so the low-limit for input for the circuit to enter max. (50%) pulse width is about 11.1V.
I think the transistors do not enter the saturation region since the output voltage is always >8V (they should remain fully open at this point). I can post pictures too.
Any tips for improving efficiency?
And btw. very nice forum
sg3525 will work from 8v to 35v , it is better to check the low volt and shutdown the controller, the pwm max will be 49%, you can add a deadtime resistor to increase deadtime.
you can improve the performance by designing proper transformer, core , winding , coil ( about 32khz with 1st schematics and about 55khz with 2nd schematics(having deadtime resistor))
you can improve the performance by designing proper transformer, core , winding , coil ( about 32khz with 1st schematics and about 55khz with 2nd schematics(having deadtime resistor))
Thank you for your answer! The layout is done so changing the circuit is not easy.
But for the original question: is it dangerous if the controller tries to keep the voltage up by raising the duty cycle to ~50%? As far as I know about transformers, they only propagate the power (from primary to secondary circuit) that is needed on the secondary side but is this true in real world? It did not seem harmful when I measured it - nothing heats up and the voltage supply current does not go up. Still I don't really understand why
But for the original question: is it dangerous if the controller tries to keep the voltage up by raising the duty cycle to ~50%? As far as I know about transformers, they only propagate the power (from primary to secondary circuit) that is needed on the secondary side but is this true in real world? It did not seem harmful when I measured it - nothing heats up and the voltage supply current does not go up. Still I don't really understand why
A DC to DC converter that has a regulated output voltage is, more or less, a constant power device. If the input voltage goes up, the average input current will decrease. This means the duty cycle will also decrease. If the voltage goes down, you have the reverse situation.
In a push pull circuit the duty cycle must never reach (exactly) 50%, because there must be some dead time to ensure both power transistor are not on at the same time.
If the power supply is properly designed, the transformer should not saturate at the maximum duty cycle.
In a push pull circuit the duty cycle must never reach (exactly) 50%, because there must be some dead time to ensure both power transistor are not on at the same time.
If the power supply is properly designed, the transformer should not saturate at the maximum duty cycle.
OK well dropping the input voltage seems to increase the current so the power stays constant. Well I guess I don't have problems until I see smoke . I guess the ETD39 core is not saturating but I think I should also calculate/measure that to be sure. However, it is not getting warm.
Any suggestions for replacing the transistors? I use now IRF1010N that have max. Vds=55V and the peaks now on drain reach about 63V p-p (or is this OK if the peaks are really short = avalance current stays small?). I can change the snubber capacitors to larger ones but that in turn degrades the efficiency and the snubber resistors are quite hot already.
. I guess the ETD39 core is not saturating but I think I should also calculate/measure that to be sure. However, it is not getting warm.Any suggestions for replacing the transistors? I use now IRF1010N that have max. Vds=55V and the peaks now on drain reach about 63V p-p (or is this OK if the peaks are really short = avalance current stays small?). I can change the snubber capacitors to larger ones but that in turn degrades the efficiency and the snubber resistors are quite hot already.
If you have got spikes that reach 63V (might be higher but one need a fast scope to detect it) I would think there is something wrong. When properly designed, there should not be any spiking.
Spiking is tamed with the damping network (cap+resistor, C1+R1 and C2+R2), but with excessive spiking, I would suspect there is something wrong with the core (leakage inductance maybe).
(With SG3525 the pulse with will never be higher than ~45%.)
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Spiking is tamed with the damping network (cap+resistor, C1+R1 and C2+R2), but with excessive spiking, I would suspect there is something wrong with the core (leakage inductance maybe).
(With SG3525 the pulse with will never be higher than ~45%.)
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Oh I thought the spikes are mostly due to the inductance of the core itself . I have understood that there always are some sort of spikes and that they are nothing to worry about as far as they are within the maximum ratings of the transistors. And that snubbers are used to dampen the spikes but not of course to wipe them away totally. I will post a picture of the spikes later.
Could you suggest any good internet sites that would explain these things in a nutshell?
Maybe I should read a bit more about inductors/transformers/smps'. An interesting area however!
. I have understood that there always are some sort of spikes and that they are nothing to worry about as far as they are within the maximum ratings of the transistors. And that snubbers are used to dampen the spikes but not of course to wipe them away totally. I will post a picture of the spikes later.Could you suggest any good internet sites that would explain these things in a nutshell?
Maybe I should read a bit more about inductors/transformers/smps'
. An interesting area however!Thanks for the site. Wikipedia also explains those things quite thorough. Have to read more but the SMPS seems to work and the class-D amp that the SMPS feeds works too So nothing to fix yet. Maybe later
How does the overvoltage over drain-source affect the transistor? Does it break it instantly or as in diodes, only overheating caused by the current caused again by the over voltage breaks it???
Any tips/sites for winding the transformer well (to avoid the leakage inductance)?? It is just a bit difficult to remove the transformer for rewinding it once it has been soldered to its place The transformer is ETD39 with 3F3 core.
So nothing to fix yet. Maybe later How does the overvoltage over drain-source affect the transistor? Does it break it instantly or as in diodes, only overheating caused by the current caused again by the over voltage breaks it???
Any tips/sites for winding the transformer well (to avoid the leakage inductance)?? It is just a bit difficult to remove the transformer for rewinding it once it has been soldered to its place
The transformer is ETD39 with 3F3 core.That sounds scary. Do you mean they could latch-up or something (I have fuses though )?
The transistor that I'm using is IRF1010N and it is "fully avalanche rated" and the max avalanche current is 43A and energy is only limited by the junction temperature. So I guess I will still try these transistors until they fail (hopefully not catastrophically). I read that after avalanche the Vds is clamped. But I will report if my amplifier cathes fire or something 
)?The transistor that I'm using is IRF1010N and it is "fully avalanche rated" and the max avalanche current is 43A and energy is only limited by the junction temperature. So I guess I will still try these transistors until they fail (hopefully not catastrophically
). I read that after avalanche the Vds is clamped. But I will report if my amplifier cathes fire or something When the voltage becomes to high between drain and source, the MOSFET will turn on. This happens when it is suppose to be off. This can cause alot of trouble, and catastrophic failure is one likely scenario. The IRF1010N is guarantied to sustain 55V between drain and source. How much over this limit that the true limit is, is unknown but it is newer a good idea to push it beyond what is stated in the data sheet. Normal and good practice is to stay quite a bit below.
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IRF app. note. On page 7 figure 7 shows a diode-like behavior on Vds - the current rises rapidly after certain voltage but the voltage remains the same. I sent them a question about this. It would be nice to know for sure however, since many sources suggests that the transistor really turns on due to positive feedback in the transistor structure. I have no idea which is true
Another IRF document:
"Some designers do not allow for avalanche operation; instead, a voltage derating is maintained between rated BVDSS and VDD (typically 90% or
less). In such instances, however, it is not uncommon that greater than planned for voltage spikes can occur, so even the best designs may
encounter an infrequent avalanche event. One such example, a flyback converter, is shown in Figures 1-3.
During MOSFET operation of the Flyback Converter, energy is stored in the leakage inductor. If the inductor is not properly clamped, during
MOSFET turnoff the leakage inductance discharges through the primary switch and may cause avalanche operation as shown in the VDS, ID, and
VGS versus time waveforms in Figures 2 and 3.
In this application, built in avalanche capability is an additional Power MOSFET feature and safeguards against unexpected voltage over-stresses that may occur at the limits of circuit operation."
So now I am quite certain of the fact that the FETs are good for my device with leakage inductance etc. Now should have time to test it properly
"Some designers do not allow for avalanche operation; instead, a voltage derating is maintained between rated BVDSS and VDD (typically 90% or
less). In such instances, however, it is not uncommon that greater than planned for voltage spikes can occur, so even the best designs may
encounter an infrequent avalanche event. One such example, a flyback converter, is shown in Figures 1-3.
During MOSFET operation of the Flyback Converter, energy is stored in the leakage inductor. If the inductor is not properly clamped, during
MOSFET turnoff the leakage inductance discharges through the primary switch and may cause avalanche operation as shown in the VDS, ID, and
VGS versus time waveforms in Figures 2 and 3.
In this application, built in avalanche capability is an additional Power MOSFET feature and safeguards against unexpected voltage over-stresses that may occur at the limits of circuit operation."
So now I am quite certain of the fact that the FETs are good for my device with leakage inductance etc. Now should have time to test it properly
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