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Old 25th April 2010, 08:18 PM   #1
moro696 is offline moro696  Romania
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Default Question regarding a PFC output cappacitor selection

Hi all, i am working at a PFC stage ratted at 3kw output power for a switchmode power supply running at 100khz in fullbridge mode
My question is, the Total Hold Up time wich usually in datasheets i see to be arround 20ms, but to achive this THD at 20ms the cappacitors usualy give very large values. I saw in some aplication notes that it usualy takes 1uf per Watt.
But if i decrease this THD in some manner let's say 800uS wich i think is enugh to supply the folowing smps knowing that conduction time in that smps running at 100khz is lets say maximum 20uS conduction.
What do you think ?
I'm saying this coz big cappacitors at 400-450V rated are expensive and large space is required for them on the pcb
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Old 25th April 2010, 09:51 PM   #2
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How much ripple can you tolerate?

800us is a pretty small fraction of 100/120Hz line frequency.

Obvious solution: at 3kW, capacitors are typically chassis mounted computer grade units, not PCB mounted.

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Old 27th April 2010, 12:10 PM   #3
iand is offline iand  United Kingdom
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Quote:
Originally Posted by Sch3mat1c View Post
How much ripple can you tolerate?

800us is a pretty small fraction of 100/120Hz line frequency.

Obvious solution: at 3kW, capacitors are typically chassis mounted computer grade units, not PCB mounted.

Tim
For SMPS almost nobody uses one or two large chassis-mounting capacitors, even at 3kW or above -- they use a large number of smaller capacitors, almost always PCB mounted.

This gives much lower inductance, and usually higher ripple capacity and lower cost for a given total capacitance (heat dissipated through surface of capacitors, several small capacitors have more surface area than one big one)

Ian
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Old 28th April 2010, 03:12 PM   #4
moro696 is offline moro696  Romania
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i agree with iand, i planned to use 10 pieces of 470uf at 400dc at the output of the pfc, but still i want to reduce that cappacity in a manner that i can reduce the pcb dimensions. And i want to know if a short hold-up time will afect the good running of the smps with a thd somewhere at 1-5 ms instead of 20ms
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Old 28th April 2010, 04:33 PM   #5
stoc005 is offline stoc005  United States
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Try it with fewer caps......but leave room on the PCB, since there will be more than a few caps, for the correct number of caps to reach 20ms. Engineering is all about experimenting sometimes and doing things nobody else has attempted/contemplated. Mistakes are learning experiences and quite valuable, IMHO. You learn nothing from success.
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