Help on 2400W Phase Shift PSU
I am designing a 2400W phase shift power supply and I have some problems that I don't understand.
The SMPS is a 24V 100A (150A peak current), it is connected to a buck-type
3phase PFC that I designed and that works perfectly (98.5% efficiency at 2500W out). The PFC stage delivers a 385V DC supply to the phase shift stage; the low voltage supply (VBSEC) is a 15Vdc supply derived from a small flyback SMPS connected directly to the rectified mains.
It seems I have a problem with the pulse transformer TR2. If the SMPS works in open loop (full duty cycle) everything is fine; as soon as it starts regulating
the output voltage the gate waveforms of Q12 and Q14 becomes DC biased (they are not symmetrical towards SGND). When this happens it seems that the synchronous rectifier goes crazy and close at the wrong time generating huge current spikes into the transformer. This behaviour is particulary critical between no load and around 5A load. The SMPS does not blow up but ugly sounds are generated by the transformer and the primary current hits the current limit point set at 18Apeak.
I think that the problem is located in the gate driver; I have already tried to change the gate resistors and removing the secondary snubbers (C26-R34) with no success.
I have found on Ti website an app note regading the asymmetry of outc-outd during duty cycle variations. I have applied the fix described in the app-note with no success.
Does anyone of you have experience with phase shift SMPS and in particular with UCC3895 controller?
If anyone has useful ideas to share with me it will be highly appreciated.
Other useful data:
Transformer TR1: EE55 core no gap, primary 21turns, secondary 4turns
Inductor L4:EE25 core with ~1mm gap, 8turns
Pulse transformers TR2,TR3: 10turns, trifilar wound on 16mm ferrite core
Current doubler: L5, L6: 13turns on kool-mu 50mm toroidal core
Sensing current bidirectionally that way with a single transformer does not work, it results in asymmetrical operation because the current transformer can't sense DC errors (it will tend to saturate in the direction of the DC error). So any DC error will not only impair AC sensing but DC sensing too (by sensing less current in the direction more is flowing.
Use either 2 transformers (one for each direction), one transformer unidirectionally with duty cycle limiting for reset, or shunts with a pole on sensed voltage drop for parasitic inductance compensation.
What Eva said. I think one of the earlier 3875s actually had that cs xfmr in series with the main transformer. Won't work.
You can use 1 transformer and measure the current in FET A and B drain. At full duty cycle there's almost no reset time so voltage spikes can be quite large.
You can also use 2 xfmrs, one in the FET A source and the other in FET B drain and sum them on the secondary side.
I've used both methods in converters with good sucess
You can also get rid of the caps in series with the power xfmr.
Also don't use the CS pin for the main current limit but rather as a save me. It's not very graceful.
Clamp the current command signal (output off error amp) to get a nice smooth peak current limit.
Oh, I didn't see the capacitors in series with the transformer. They will actually make the circuit malfunction with current mode control, they only work with voltage mode control.
in fact without the series blocking capacitor the trasformer saturates due to DC. Theoretically using current mode control this capacitor is not required but in my case it is absolutely needed.
In fact this current transformer connection comes from an app note of the old
UC3875, the new designs with 3895 connects the current transformer between the two mosfet drains and the power supply input.
In my design the operating duty cycle is around 65% and to connect the current tranasformer in this way I must be sure to fully demagnetize it in the
interval when both upper mosfets are off, otherwise it will saturate.
I have tried to disable the synchronous rectifer (I removed the drive signal and I use only the mosfets body diodes) and the SMPS at light load still make nasty sounds from the transformer, the drive signal of C and D mosfet is sill not symmetrical wrt. to GND. In those conditions the DC voltage across the transformer DC blocking capacitor reach 40-50Vdc; when the load is increased the DC voltage becomes much lower (<5V).
I think that my brigde is unbalanced but the question is:
is the bridge unbalanced because of drive issues or it is unbalanced because of a wrong current sense signal due to current trasformer position?
What about running the UCC3895 in voltage mode instead of peak current mode control?
I know that there will be for sure an imbalance in the brigde that creates a DC offset, but that offset will be cancelled by the coupling capacitor.
The output current will not for sure exacly share at 50% over the 2 current
doubler inductances due to imbalance but is it so important?
I have seen some industrial applications running the UCC3895 in voltage mode with a current doubler rectifier and they works ok.
If I run in voltage mode I can even leave the current transformer as it is now since it will be used only for peak current limiting and for adaptive delay set (not so critical). Changing the position of the current transformer is very difficult for me on the current layout and I prefer to avoid it if possible.
Awww. Don't give up. Current mode works great with this topology...something is wrong. FIND IT!!
Take the series caps out. It will never work in CM with them.
What does the ramp signal look like at the chip? This signal cannot be currupted at all. Make sure that you have single point connections from the cs xfmr to the chip grnd so that you;re not picking up noise.
You said that you see drive signals that are not symetrical at no load. This is an indication of the 'save me' CS trip. If you isolated the CS pin and short it for an experiment does this go away or blow up?
You can also add more slope to help at the lower loads. Not too much or you'll be operating closer to voltage mode.
Good idea about getting rid of the sync FETS for now. Strip out anything that can cause problems and just worry about what wrong or you can be chasing your tail.
Also. Have you just tested the power stage? I know you said you ran in open loop but what about open voltage loop but closed current loop?
Get rid of the voltage op amp and feed in a DC signal into the EAP of the chip. A potentiameter tied to 5V ref works good. Consider this your current command signal. Set your load to full load and adjust the pot from zero voltages upward.
You should now be able to operate the converter in a current source fashion with the current set by the pot. The output voltage will vary.
If you can get this mode to work you're on a good track and most likely it's a loop thing.. If this does not work then there's really something wron.
I have tried to check the current loop using the current error amplifier.
If I put a direct short on the output the behaviour is quite unstable with the
CS 'save me' tripping sometimes. If instead of a short I put a very small resistor (around 0.1ohm) everything looks fine and I can regulate the output current.
Sorry I did not tell you that there is another op amp connected to VFB that closes the loop using the information from the output current hall sensor to regulate the output current. This is not for sure the root of the problem because even if I disconnect it the behavior does not change.
The signal on the RAMP pin is quite bad, especially at low load when the ramp
coming from the CS transformer is not well defined. I tried to increase the amount of slope compensation but it does not help.
I tried also tu put the chip in voltage mode and everything seems ok: no more instabilities at low load, no nasty sounds and no brigde imbalance.
I have mesured the DC voltage across the transfomer series cap and it remains below 0.2V from no load to around 50A load.
Now I am supplying the converter with a 200V 1000W laboratory power supply (I am not using the PFC) and I have regulated the output at around
12V instead of 24V. I have done this because if something goes wrong I have the 200V power supply current limit that saves me and I avoid to blow up everything...
I have not tried to short the CS and see what happens; if t blow up in a bad way with such power there is the risk to burn the PCB traces and I have only one prototype available.
Btw: what you call the 'Save me' protection of the CS means the second trip point at 2.5V or other?
I think now that the problem is in the current transformer; good hint to route the transformer GND directy to the chip GND, now it is connected on a common GND plane on the PCB and there is the possibility of noise pick up.
Removing the series cap is not possible, if I try this there are some loads (not only a low load but also at heavy loads) where the transformer saturates and the CS trips in.
Going in voltage mode seems to solve all my problems, so why don't go for it? What are the possible problems?
When in voltage mode I have also tried to reconnect the synchronous rectifier and everything goes well. The only problem is that when the mosfets body diodes conduct there is a huge ringing voltage spike on the output mosfets drains; an RC snubber is for sure needed here.
Next week I will do some new test changing the position of the current transformer (between the positive rail and the upper mosfet drains) using current mode control with no series cap. But before doing this I need to damp the ringing on the syncronous rectifier, now with 200V input the spikes reaches around 70V and the SR mosfets are rated 100V. When I power up with the PFC (385V) those spikes can reach the mosfets BVDss.
Thank you for your support
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