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Old 11th April 2010, 08:03 AM   #21
ontoaba is offline ontoaba  Indonesia
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Since it using phase shift, single switch will be amount of power that need to be dissipated.
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Old 11th April 2010, 08:52 AM   #22
ontoaba is offline ontoaba  Indonesia
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oboy,,, its single hour left I am thinking about this, trying to find some of the problem way.
May be you should use current mode, with current limiting it is able to reduce the pulse width, may be need to change the controller too.
I am really don't have any idea.
May be she could help you, or another.

And may be that inductor will always hot.

Last edited by ontoaba; 11th April 2010 at 09:09 AM.
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Old 12th April 2010, 04:55 PM   #23
savu is offline savu  Romania
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sorry I can not share the PFC schematic but I can tell you more or less how I did it.QUOTE]

Hello Mag.

What I want to acomplish is to use a dc motor as a dc generator. The motor is rated at 5KW. But in order to get the smooth output voltage i have to have constant rotation and the problem is that i will not have constant rotation since i'm going to drive it with a steam turbine.

More wood = more power.

But in order to use that power i need a steady 400VDC output so that i can invert it in 3 sine waves at 230VAC each. so after some searching I came acros the buck converter (PFC).

The rating of this buck converter (pfc) should be:

min 100Vdc
max 400Vdc
avarege current 12.5A

max current 12.5A

The avarage input curent is actualy the maximum output curent of the generator, because I don't thing that if the generator is at half the speed (power) it would generate more that 8A.

I plan to use Force Conduction Mode for the PFC with very tight PCB and fiber optic drive (TosLink) to FET or IGBT, force air cooling, gapped litz wire E inductor and all of this monitored by a microcontroler for protection.

So from you're experience ...

Am I going the right way?

1'st rule of chess:
The only way to get smarter is by playing a smarter opponent.
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Old 14th May 2010, 05:18 PM   #24
mag is offline mag  Switzerland
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Default Snubber Issue

Hi all,
I am continuing my project of the 2400W PSU and I have a problem with the secondary snubber.

Measuring the waveform across the output sync. rectifier mosfets I found a squarewave with a flat at around 75V and an overhoot at mosfet turn off of around 120Vpeak with some 10MHz ringing.
My mosfets (IRFB4310Z) are rated 100V so I am finding a way to clamp the
overshoot below 100V.

I have placed an RC snubber in parallel with the transformer secondary and the best compromise seems to be 2.2nF+33ohm. This will damp the ringing
but it does quite nothing on the overshoot.

I have tried several ways to clamp the overshoot:

1) put a 1.5ke100ca (bidirectional TVS 100V) in parallel with the transformer secondary. With this the overshoot becomes around 115V but the TVS becomes very hot.

2) put 2 1.5ke100a (unidirectional TVS 100V) in parallel with the sync. rect. mosfets (same orientation as their body diodes). The overshoot is still at around 115V but the TVS blow up after some minutes due to overtemperature. I think that the TVS is conducting in the forward direction and it contributes to the load current. So....

3) put 2 1.5ke100ca (bidirectional TVS 100V) in parallel with the sync. rect. mosfets. The overshoot is still at around 115V but there is no more forward conduction of the TVS. It is still very hot (120C) after some minutes.

4) put an R-C-D clamp in parallel with the sync. rect. mosfets. with
D=MUR160, R=10k, C=68nF. The overshoot is clamped at 110V and the power dissipation in the resistors is around 1W per resistor. To reduce the overshoot below 100V I must use lower values resistors, but the dissipation becomes very high. For example with R=1k the overshoot is 93V but the dissipation is around 10W per resistor!!

My questions are:

- Is it dangerous to run at 110Vpeak (for around 150ns) on a 100V rated mosfet? The mosfet will not for sure enter in avalanche mode.
- Is there a way to build a non dissipative (or less dissipative than 20W) snubber acting as a voltage clamp?
- My overshoot comes from the transformer leakage inductance referred to the secondary side. Does it includes also the inductance I have in series with the primary? If yes reducing the value of that inductance will reduce the stored energy and thus the overshoot at the expence of running in hard switching at light loads.

Please help.

thank you

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Old 14th May 2010, 05:45 PM   #25
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avalanche rated MOS-FET's such as those used in PDP applications are guaranteed for 20+% VDS. the TVS is indeed a slow zenner diode. although unpractical, you might consider using a shotky diode in series with TVS and a nF range cap in parallel with TVS. how about the MOS-FET turn on time? too fast can lead to large ov. shoot due to parasitic inductances. if the layout is not the final one you might consider reducing the parasitic inductances to minimal values, even if need to solder the MOS-FET's legs as close as possible to the case, but in this case pay attention to the mechanical issues which may lead to long-time reliability problems due to increased mechanical stress close to the device pins.
consider using an active clamp which can recover most of the energy and redirect to the load.
try to reduce the transformer lk inductance by using a copper shield around the transformer.
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Old 15th May 2010, 01:10 AM   #26
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Leakage inductance is your friend using this topology. In fact you should be designing the xmfr for high leakage to keep the shim to a minimum.

Yes the shim choke is reflected back to the secondary as leakage but that's probably not your problem. I would look at layout.

You can also try to find fet with faster diodes or schottkys. Internal or adding them external.

Can you find 150V fets instead and don't worry about the spike?
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Old 17th May 2010, 08:32 PM   #27
mag is offline mag  Switzerland
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Exacly, leakage indutance is my friend and I can not minimize it. I need around 12uH for ZVS, 7uH in the transformer Llk + 5uH external.

Now I am using 100V rated mosfet with the following characteristics:

- IRFB4310Z
- Vdss=100V
- Id=120A
- Rds_on=4.8-6mohm
- trr=40ns
- Qrr=58nC

I use 3 in parallel for each SR leg.

My overvoltage spike tops at around 110V without any clamp (just RC snubber for ringing).

There are the following possibilities changing the mosfets.

1) Infineon-IPP048N12N3G
- Vdss=120V
- Id=100A
- Rds_on=4.1-4.8mohm
- trr=113ns
- Qrr=315nC

2) Infineon-IPP075N15N3G
- Vdss=150V
- Id=100A
- Rds_on=6.2-7.5mohm
- trr=146ns
- Qrr=478nC

For Infineon parts I see a much higher figure for body diode trr and Qrr compared than IRF parts. It is true that the figures are measured in different conditions but the difference is huge.
On top of that the Rds_on is higher for the 150V parts and probably I will need 4 mosfet for each leg to lower the losses.

Who can guarantee me that even using 150V mosfets the overvoltage spike does not increase over 150V due to the Qrr difference?

The voltage waveform on the mosfets drains is basically the same at full load or at light load. I have tried to put 2 MBR20200 (200V 20A) Schottky diodes in parallel with the mosfets but the waveform does not change at all.

I have seen on some app notes that adding some capacitance across the gate and drain of the mosfets can reduce the spike. I don't understand that, can someone explain me this? BTW I did not noticed any difference in putting up to 200pF across G-D.

If I look in detail the drain waveform with no RCD clamp I see that the peak is flat for around 150ns at around 120V and then the ringing starts. It is a sign that the mosfet is entering in avalanche mode?
Exept from this everything is running good and I have let the power supply run at 100A load for more than 2hours without problems.


You say to look at the layout but what should I look? I have my transformer secondary connected with 2 wide power planes on the mosfet drains and on the output inductances. On the bottom layer I have a plane for the GND return. Now my snubber + RCD clamp is mounted flying over the transformer and GND plane trying to keep the leads as short as possible.

Does the primary side layout make some difference? In any case I have a series inductance of 5uH (the shim) and even if the primary traces are long they are for sure less important than the contribution of Llk+Lshim reflected to the secondary side.

Any comments?

thank you
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Old 18th May 2010, 12:47 AM   #28
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Layout should be tight. Wide fat traces. Large gnd plane. Looks like you have it. Do you have pics of the layout?

What happens if you short the shim choke? Does the output spike get reduced? The problem with having alot of external shim inductance is that you have an unclamped node and this can cause resonances and it*may* reflect back on the output. I haven't done a zvs in years and my memory isn't like it used to be.
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Old 18th May 2010, 01:01 AM   #29
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Leakage inductance is preferable to be minimized on the transformer and added externally as a series inductor. there are few reasons for that, especially in massproduction where is easier to control the Lk. inductance just from the series inductor. there are at least a dozen of ap notes where they mention this fact. also the size of the transformer can be smaller, as an example are the transformers used for LLC converters, which have the largest Lk inductance, usually 1/5-1/8 the magnetizing inductance. their size is larger than the same transformer with minimal lk inductance and separate series inductor.
what values have the gate drive resistors ?
have you tried to use an active snubber ?
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Old 18th May 2010, 08:24 AM   #30
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If I look in detail the drain waveform with no RCD clamp I see that the peak is flat for around 150ns at around 120V and then the ringing starts. It is a sign that the mosfet is entering in avalanche mode?

Mag, that's right. It is being clamped by drain-source breakdown. It begins to ring once the voltage drops below that level.
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