SMPS EMI Stage

[microsim444]

Originally Posted by opc

Microsim:

I'm a little worried now... the Y-caps need to go to chassis, and I don't see any 6mm isolation on that PCB. This is basic safety, and needs to be followed. Those caps also need to be rated appropriately. The exclamation mark and triangle are on the schematic for a reason.

If you're not familiar with basic off-the-line switcher safety, I would strongly suggest you read up on it, and strongly suggest you not attempt any project that is beyond your abilities in the safety department.

If it ever caught fire and burned your house down, your insurance company would laugh in your face and you wouldn't get a dime. At least if you can prove due diligence you might stand a chance.

Also, you'll probably have problems with light-load stability with a very high power SMPS hooked up to a class AB amp with light bias.

Cheers,
Owen

ok. you are right, and those are the notes i want to hear
as i know the 6mm clearance is required in the other board, not the EMI stage!

the capacitors you cant see, are added in the last pcb. and can i use the ground plan on the pcb as the chassis?

And regarding safety, I know exactly what I am doing, and I have serious protection methods before the test will began

Also I have just knew a French engineer who offered me FREE support for this project, and will assemble this supply together, since he is a SMPS engineer with 4 years experience.

So he will check every thing before that late stage ( the testing)

Also I had no problems with my previous prototype of SMPS with light-load stability, that was 900W +-100V, with the 1000W load dropped to +-82V what I mean, the voltage almost the same, but higher current!!

since no one in here offered free support for this project!

[Eva]

What consequences do you expect from having the switching transistors connected to the PCB with 15cm long wires that don't even run close one to another?

In the reply to this question is the solution to your problem

In my first off-line SMPS prototype 10 years ago I didn't even use a PCB, all was point to point and waveforms were terrible, but it could do 15V 120A regulated output. Parasitics were making things fail and that thing was capable of disturbing a CD player that was on the same room.

This may sound like a joke but now I have the opposite problem with the last revision PCBs of the class D amplifier in which I'm working: Too low parasitic inductances. During body diode reverse recovery, current slope (di/dt) depends on gate supply voltage, gate turn-on resistor and parasitic source path inductance (somebody understanding that would never use wires). The latter has become so low that it's difficult to achieve a safely low di/dt without compromises in the first two factors. Origilally MOSFET were failing at high current and high temperature because the layout was handling over 1500A/us per body diode without problem. Then I noticed that parasitic inductances were less than half of what I was expecting

Concerning the insulation practices, In the beginning I learned a lot by studying commercial SMPS of various kinds and its transformers. Much later I had access to the papers describine standards (quite dense), but I alwas understood intuitively why everybody was leaving 5 to 10mm spacing between primary and secondary side on the PCBs and margins on the transformers Sometimes I was feeling that layouts and semiconductor choices were leaving some room for improvement, but a good layout or good efficiency are not required for certifications, proper insulation is.

[microsim444]

Hi EVA,


Those wires are totally wrong, but in that design there was no enough space for the heat sink, AND that supply worked,(almost).

Test was on halogen lamp 1000W for 1 Hour with FAN. I don't know, worked.
But mosfets used to blow fast at 1000W load, at 700W worked for 5 hours!!


I understand that SMPS is not an easy project, but I need more information's to prevent too many errors.

Thank You