Considering the output inductance of around 5uH of a typical 3-terminal regulator, the bypass capacitors of 0.1uF at any opamp supply pins and other bypass capacitors, the ESR and wire resistence of the circuit boards, the effective LCR circuit will have some high Q resonance anywhere from 500kHz to 2M Hertz, depending on the values of the LCR. After spending the whole morning modelling it using LTSpice I have not found a way to get rid of resonance, unless I padded enough resistence to make the capacitors ineffective, which is pointless. If wrong capacitors are used the circuit can resonate right at the audio spectrum of 20Hz - 20kHz. I can not eliminate the resonace. I can only push it to 500kHz or above.
Does it matter to have a power supply high Q resonance at 500kHz or above? Would the opamps overheat? Would there be other problems?
Regards,
Bill
Does it matter to have a power supply high Q resonance at 500kHz or above? Would the opamps overheat? Would there be other problems?
Regards,
Bill
You might have heard that designing a linear regulator is just like designing and amplifier. This is true in most ways.
A properly designed amplifier will not have resonances or load preference (or if it does it will be to a minimal level).
With a linear regulator, the output impedance begins to increase above a certain frequency. At that point, we add a bypass capacitor (aside from the decoupling caps if you want more performance). If the value of the cap is large enough, the cap will take care of the HF signals instead of the regulator. So in short, if you want to help get rid of resonances, why not try say, a 390u bypass cap (in addition to the decoupling cap)? This is relatively easy to see the effects of in LTSpice if you run an AC analysis. In my playings with the simulator, sometimes values of 10mF were necessary to remove the HF impedance increase, with my worse designs! The necessary value of this cap will depend on the regulator's load rejection and its HF characteristics. For one of the chip regulators this cap shouldn't have to be too large.
I think what I'm saying is relevant to the topic.
The capacitance multiplier will probably be a factor. However this albeit large capacitor will have a relatively large ESR because of the transistor's transconductance. Surely someone will correct me if I'm wrong?
As far as resonance, you will certainly have a problem if the opamps are oscillating. But in order to start a resonance, you have to supply at least for an instant some energy at the frequency of the resonance. If you use a switching supply, perhaps induced spikes could cause this ringing (perhaps an application where linear supplies are handy?). If your box isn't shielded, interference from other apliances could potentially instigate the resonance. I don't have experience with these things though.
- keantoken
A properly designed amplifier will not have resonances or load preference (or if it does it will be to a minimal level).
With a linear regulator, the output impedance begins to increase above a certain frequency. At that point, we add a bypass capacitor (aside from the decoupling caps if you want more performance). If the value of the cap is large enough, the cap will take care of the HF signals instead of the regulator. So in short, if you want to help get rid of resonances, why not try say, a 390u bypass cap (in addition to the decoupling cap)? This is relatively easy to see the effects of in LTSpice if you run an AC analysis. In my playings with the simulator, sometimes values of 10mF were necessary to remove the HF impedance increase, with my worse designs! The necessary value of this cap will depend on the regulator's load rejection and its HF characteristics. For one of the chip regulators this cap shouldn't have to be too large.
I think what I'm saying is relevant to the topic.
The capacitance multiplier will probably be a factor. However this albeit large capacitor will have a relatively large ESR because of the transistor's transconductance. Surely someone will correct me if I'm wrong?
As far as resonance, you will certainly have a problem if the opamps are oscillating. But in order to start a resonance, you have to supply at least for an instant some energy at the frequency of the resonance. If you use a switching supply, perhaps induced spikes could cause this ringing (perhaps an application where linear supplies are handy?). If your box isn't shielded, interference from other apliances could potentially instigate the resonance. I don't have experience with these things though.
- keantoken
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Keantoken,
Thanks for your reply.
No manufacturers have recommended using very large capacitors at the output of the 3 terminal regulators. From LTSpice, I can easily see that a low ESR capacitor from 47uF to 470uF can create a resonance peak of up to 20dB between 500Hz to 5kHz. However, I have found that by using a large capacitor of 2,200uF in series with 0.1R at the regulator output, it can damp that resonance to below 1dB. A capacitor multiplier is even better, provided that it has low ESR.
Most op amp datasheets recommend using a 0.1uF ceramic (I use MKP 0.1uF with a 0.03R ESR) at the op amp pin for bypass. I mentioned in my first post that this creates some high Q resonance between 500k Hertz and 2M Hertz that can not be cured even with the damping as described above, when combining the 5uH output inductance of the regulator and the ESR and ESL of the bypass caps, as well as PCB track R and L. I observed them more carefully this time and found them to be more of a high Q dip than a high Q peak of 20dB magnitude. Actually, with the capacitor values I used, the resonances are at 3M Hertz. I don't know if they are harmful or not, as the amplitude should be less than 0dB.
The capacitor multiplier (CM) I used was from JLH. He claimed that the CM creates an equivalent 0.5 Farad, with an impedance less than 0.02R from 500Hz to 30kHz. So I was wondering if I should model it in LTSpice as a 0.5 Farad 0.02R capacitor.
I would like to upload some pictures from my LTSpice modelling, which would say a lot more, but unfortunately, after I changed my ISP, I have not been able to store any photos. I will work on it.
Regards,
Bill
Thanks for your reply.
No manufacturers have recommended using very large capacitors at the output of the 3 terminal regulators. From LTSpice, I can easily see that a low ESR capacitor from 47uF to 470uF can create a resonance peak of up to 20dB between 500Hz to 5kHz. However, I have found that by using a large capacitor of 2,200uF in series with 0.1R at the regulator output, it can damp that resonance to below 1dB. A capacitor multiplier is even better, provided that it has low ESR.
Most op amp datasheets recommend using a 0.1uF ceramic (I use MKP 0.1uF with a 0.03R ESR) at the op amp pin for bypass. I mentioned in my first post that this creates some high Q resonance between 500k Hertz and 2M Hertz that can not be cured even with the damping as described above, when combining the 5uH output inductance of the regulator and the ESR and ESL of the bypass caps, as well as PCB track R and L. I observed them more carefully this time and found them to be more of a high Q dip than a high Q peak of 20dB magnitude. Actually, with the capacitor values I used, the resonances are at 3M Hertz. I don't know if they are harmful or not, as the amplitude should be less than 0dB.
The capacitor multiplier (CM) I used was from JLH. He claimed that the CM creates an equivalent 0.5 Farad, with an impedance less than 0.02R from 500Hz to 30kHz. So I was wondering if I should model it in LTSpice as a 0.5 Farad 0.02R capacitor.
I would like to upload some pictures from my LTSpice modelling, which would say a lot more, but unfortunately, after I changed my ISP, I have not been able to store any photos. I will work on it.
Regards,
Bill
possibly useful links in this post:
http://www.diyaudio.com/forums/showpost.php?p=604832&postcount=7
http://www.diyaudio.com/forums/showpost.php?p=604832&postcount=7
i've seen 3 terminal regulators used in just about everything, even digital logic running at 1Mhz clock frequencies, and the only time i've seen them misbehave was when the decoupling caps were dried out and had high ESR. that said, there is usually a small amount of "hash" on a 78xx regulator when powering digital devices, but it's usually far below the level where it would cause a problem. as far as powering analog from them, i've never seen any effects that would be a problem. properly designed analog circuits would have decoupling caps all over the place, maybe not as much as with digital circuits, but definitely enough to swamp the inductive effects of the regulators.
There's an ap note on the noise peaking phenomena- I think it's in Bob Pease's book. Don't know if it's on the web or not. That's a lot different than out and out oscillation, which doesn't usually occur if you follow anywhere near the manufacturer's recommendations for the reg. Chances are that you're not modeling the caps correctly- hardly anybody does. There are some old posts on the matter, but in essence ESR can't be modeled as a constant resistance. That becomes clear when you look at the formulas for dissipation factor. In real circuitry you can kill the noise peak with some strategically placed resistance, without compromising the filtering. You can also just swamp the thing out, as the Q (1/D) will be so low as not to matter.
Using large capacitors on the output of a regulator might not be recommended because the reg can dump a lot of current into the capacitor in a small period of time (dunno if this is important for 3-T regs since most are current limited around 1.5A).
If the multiplier's output impedance is not at least lower than that of the regulator alone, then I don't think there will be a significant advantage. Modeling the multiplier as a cap and resistor as you say should work well enough.
Okay, I am familiar with capacitance multipliers (though not specifically about the JLH design you speak of). If you use a Darlington for the multiplier, about the only advantage over a single transistor will be higher current gain. Darlington configuration increases output impedance over a single transistor, and this might swamp out any advantage gained by the high capacitance. So instead, I suggest using a CFP instead of darlington. On the simulator, output impedance dropped by over a factor of 10 (with the transistors chosen, impedance of the Darlington was about 58mohms, impedance of the CFP was only 3m, and both had the same response). To put things in perspective, 3mOhms of the CFP will correspond to about 50.5db of load rejection. 60mOhms corresponds to about 24.4db. This means that say, as -40db load rejection regulator would benefit from a CFP multiplier but wouldn't gain much from a Darlington multiplier. I will post this simulation data if asked.
Why don't you build the circuit and see how large a cap it takes to remove the resonance as much as possible? With very good regulators, it actually takes a larger capacitor.
For cross-reference:
LM340: 8mOhms series resistance. -42db
CFP Cap multiplier: 3mOhms -50.4
Darlington multiplier: 58mOhms -24.4
- keantoken
Keep in mind, that you most often have also an electrolytic cap somewhere near reg's output. It should provide some usefull ESR. That's why when small bypass caps are used as well, I prefer to not use a low-ESR electrolytic.
If you need a long PCB track or are affraid of resonances or want to kill some potential resosnace for any reason, than a ferrite bead in series and/or snubber in parrallel are your friends.
You may try simulating different snubbers and ferrite beads, the latter should be more helpful in killing track inductance problems.
PSU resonances are real pain for audio, mainly in respect to opamps and DACs, they do matter several octaves above 20kHz and taming them can be vital, that is one of "easier heard then directly measured" things.
P.S. 5uH from a regulator is hardly a real inductance
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Thanks for contributing.
I have managed to upload some pictures now.
I understand very well that my modelling is never accurate. There are too many variables to make it reliable. But it is quicker to do it this way to examine possible resonances comparing to manually calculate in the way of F = 1.00 / (2 * 3.1415926 * sqrt(L * C)), Z = sqrt(L / C), etc.
I draw the circuit in LTSpice and see the frequency response to AC, by which I guess where the resonances are. I understand such modelling is very limited.
I have managed to upload some pictures now.
I understand very well that my modelling is never accurate. There are too many variables to make it reliable. But it is quicker to do it this way to examine possible resonances comparing to manually calculate in the way of F = 1.00 / (2 * 3.1415926 * sqrt(L * C)), Z = sqrt(L / C), etc.
I draw the circuit in LTSpice and see the frequency response to AC, by which I guess where the resonances are. I understand such modelling is very limited.
The image below shows how a 1u ceramic at the output of a 3-T reg creates a huge peak at just above 70kHz.
An externally hosted image should be here but it was not working when we last tested it.
Replaced the ceramic with a 4.7u Tant.
An externally hosted image should be here but it was not working when we last tested it.
Replaced the Tant with a Rubycon ZL 100uF. The datasheet indicates that at 100kHz the impedance is 0.13R. At that frequency the 0.13R should include the ESL. At lower frequencies the ESR would be higher but should not be significantly so above 500Hz. So I just put in 0.13R ESR to see how it looks. Of course, in real life, it can be far way out, due to temporature, this and that.
An externally hosted image should be here but it was not working when we last tested it.
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Added a Rubycon ZL 2,200uF with 0.015R Z at 100kHz. I would pad the resistance to 0.1R. This damps the resonance created by the 100uF ZL.
I learnt this from reading a paper a while ago, that using a very large capacitor with appropriate resistance can damp some LCR resonances.
So far so good.
I learnt this from reading a paper a while ago, that using a very large capacitor with appropriate resistance can damp some LCR resonances.
So far so good.
An externally hosted image should be here but it was not working when we last tested it.
My attempt to model the JLH ripple eater / C Multiplier in the PSU. JLH does use a darlington. But he demonstrated in his graphs and in his text that the impedance depends on the capacitors used, which were 2 x 2,200uF. So the impedance should be as low as 0.008 at 100kHz with 2 x Robycon ZL 2,200uF. JLH claims that from 500Hz to 30kHz the impedance is below 0.02R.
An externally hosted image should be here but it was not working when we last tested it.
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Now here comes the trouble. As soon as I add a 0.1uF MKP for the local bypass, see what happens at 3.5M Hertz!
In the graph, the resonance seems to be 70dB down, but remember that such modelling is not accurate. 70dB down was only because I assumed that the ESL was constant at 20nH. At high frequencies, the ESL will be way way higher so that in real life the Low Pass filter would never be looking like what is in the graph.
So it comes back to my original question: Does resonance at 1M Hertz matter in audio? Would it cause instability? what is the consequence?
In the graph, the resonance seems to be 70dB down, but remember that such modelling is not accurate. 70dB down was only because I assumed that the ESL was constant at 20nH. At high frequencies, the ESL will be way way higher so that in real life the Low Pass filter would never be looking like what is in the graph.
So it comes back to my original question: Does resonance at 1M Hertz matter in audio? Would it cause instability? what is the consequence?
An externally hosted image should be here but it was not working when we last tested it.
Resonance means that voltage is in phase with current and there is absolutely nothing evil nor bad in it. If you get a series resonance in reservoir/filtering network, than lucky you, if there is a parallel resonance, take care of Q to get low bump in transfer. Theory is as simple as it gets.
The real thing is minimizing negative effects on the real circuit by aware use of snubbers and ferrite beads (I don't repeat that without a reason) and observing a waveform while simulating a current step source.
The real thing is minimizing negative effects on the real circuit by aware use of snubbers and ferrite beads (I don't repeat that without a reason) and observing a waveform while simulating a current step source.
Your problem with capacitors does this relate to a particular design problem like is it an analog circuit or is it a digital circuit. In practice very good audio designs only use one capacitor of decoupling normally a non low esr type, because capacitors today are good and quite often dont need a plastic 0.1uf cap etc in parallel which can cause resonance . If a capacitor does cause a resonance a small resistor is series is added.
Regards
AR
Regards
AR
The app note "Understanding and reducing noise voltage on 3-terminal voltage regulators" by Erroll H. Dietz is in App C of Pease's book "Troubleshooting Analog Circuits".
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