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tstitans 3rd August 2009 04:01 PM

Voltage spikes under load
Hi all.

I posted on here before with questions asking about potential high-powered SMPS problems.

I've been working on making my 50W supply capable of higher power. It's a full bridge topology now, runs fine with resistive and lower capacitive loads up to around 150W, which is exciting in itself. I'm using a voltage doubler and diode bridge to take incoming 110Vac to and convert it to 2 DC lines: 170 Vin+ and -170 Vin-. This then gets fed into a full bridge (2 pairs of MOSFETs), switching at 100kHz, which alternates +/- 340V across my transformer (ee-55x2).

Now, when I increase beyond this 150W too much, I suddenly get all my FETs blown...before the fuse blows, they all are broken (straight short between all 3 pins). I only have 1 differential o-scope probe, so these captures don't show actual Vgs on both sides (As I can't ground the -170V line through the scope), but I do have the second probe on the complementing gate drive pins of the PWM. The rounded wave is a straight differential between gate-source (Vgs) at the pins a MOSFET in pair A, and the squarish wave is the OutB at the PWM (gate drive signal for pair B), with 10V/div on both.

No Load:


My guess is that as I increase the current or voltage, these spikes/noise causes, at some point, both sets of FETs to turn on, thereby causing a straight short from Vin+ and Vin- (340V) through the MOSFETs. I'm not a super-experienced designer though, so if you have any other ideas, I'm all ears.

Also, I have 2 questions:
1) what causes these? I have an output inductor in series with the load, so I think the spike is the output inductor and the transformer inductance responding to current. It's hard to see on the square wave, but the noise isn't at the beginning of the wave or Vgs ramp...if I zoom in, it corresponds to the little slope change on Vgs, which I believe corresponds to MOSFET turn-on (~4V), or when current starts to flow. Putting the scope on the output of the transformer shows that the Vout ramp occurs at the exact time of the spike (ie. a short time after the Vgs ramp starts - there's a delay between the beginning of the gate drive signal/Vgs increase and the beginning of the Vout) I could be completely wrong about the causes though...

2) I have snubbers across the FET drain-source, which I found experimentally as the most noise-reducing of anything I have laying aruond. If I put one on the transformer secondary across Vout, would that help? If so, what values should I use? (zooming in on the noise, I got a 150ns wavelength at any substantial load) I've tried experimentally with a few different RC values with no effect. I've also read that I may need snubbers across the rectifier bridge diodes, although I don't understand that at all.

3) I haven't put a filter capacitor on yet, maybe that will help improve or negate this noise...I didn't think it would because I've read that a capacitor along only changes the frequency of the noise, not the length (ie. a snubber needs a resistor to decrease ringing lenght) .... any suggestions for that? I don't know the calculations involved in capacitance needed for ripple control.

Any info or suggestions would be greatly appreciated.

luka 3rd August 2009 06:18 PM

Your gate waveform [green?] is bad, this should be 100% squere

And those spikes or oscilations are from transformer leakage inductance. You have wrong values of RC snubber probably and most od it, not across fets but transformer itself, and yes primary and secondary helps a lot

And all pins short, if you have 2 fets turned on at the same time, wrong fets..

And btw, you kill ringing with R not C :smash:

darkfenriz 4th August 2009 01:49 PM

Try scoping the difference between ground potential at both sides.

gootee 13th August 2009 02:01 AM

There is a good paper about snubber design on the Cornell Dubilier website, at , in the technical papers section:

There are some other good ones on line, too:

I haven't tried most of those links for quite a while. I hope that they still work.

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