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Bootstrapper 27th July 2008 09:24 AM

Difficulties with SEPIC converter

I designed the following SEPIC converter for experiments with the solar panels I'm soon buying. The schematic diagram, both copper drawings and the assembly drawing are added to this message. The solar panel system I spoke of consists of two 100 W panels (Voc~20 V, Isc~10 A), so one knows pretty sure the worst case conditions. Basically, you cannot draw more current from the panels than the rated short circuit current is.

Anyway, this converter works perfectly when there is a small load at the output (the output voltage is set to 14.4 V). But when I start to draw more current through the converter from a 12 V test supply, an irritating noise appears, and it gets louder as the current increases. So I thought the inductor core must be saturating. It isn't maybe made clear in the schematic, but the two inductors are wound on the same core, E42/21/20 with approx. 3 mm air gap (quite large one). I tried to simulate and calculate the inductors and core to withstand maximum of 10 A, but something has gone wrong. The inductors consist of 15 turns, two 1.2mm (diam.) enamelled copper wires wound parallel.

I fear I have made one crucial mistake: I salvaged this core from a defective SMPS, and it might be that the ferrite core itself is permanently magnetized and therefore saturates far more easily. I could fix it if I heated the core above its Curie temperature, but since that isn't an option, I guess it's time to make a new inductor set. Could there be any other reason for premature saturation? Thanks for opinions!

The schematic

The bottom copper

The top copper

The assembly

darkfenriz 27th July 2008 12:08 PM

Since in sepic there is a diode/capacitor output, you are basically sensing peak voltage, not average, the PWM loop may be unstable. Try dominant pole before VFB.
Just a thought....

Bootstrapper 27th July 2008 02:49 PM

Hi, adding a small (68 nF) cap between Vfb and ground showed just a little improvement, but the general behaviour didn't improve much. Thanks anyway!

Bootstrapper 28th July 2008 07:12 PM

Well, I did make several changes today:

-Added RC snubbers across the diodes
-Added 1 uF in parallel with the compensation loop capacitor
-Added 100 nF between Vfb and ground
-Added 1 uF between Out and ground directly after the diodes

As a result the waveforms and behaviour improved a bit. The voltage over the diodes shows still some oscillation, although rapidly damping. I can take only approx 0.5 A from a 12-V supply until the input current begins to increase and the horrible noise appears.

Could someone give any hint on this issue? Is the layout ok?

Eva 30th July 2008 08:06 AM

The "horrible noise" is the result of quick duty cycle changes due to control loop oscillation. This happens when frequency compensation is wrong. I don't have any experience with SEPIC and I don't know how you derived your compensation scheme, but there may be some mistake.

Also, two 1000uF 16V capacitors in parallel don't seem enough at all to reliably handle the ripple currents involved for 15A output, even if they are of the low-ESR type.

Bakmeel 5th August 2008 11:56 AM

Though SEPIC is a bit uncommon to use as solar array preregulator, I'm interested if you could post your findings if you make the thing work.

Bear in mind that a solar array essentially works as a voltage limited current source, and the most accurate model is to use a current source with diodes antiparallel and a series resistance.

Texas Instruments (formerly Unitrode) prepared some good reference design papers on SEPIC. Try a search on reference "SEM900". There are some links left to the control loop design.

Good luck!


Ouroboros 5th August 2008 12:10 PM

As both sections of L1 are wound on the same core (as is possible to do with SEPIC), the ripple current through the 2x1000uF caps is much reduced compared with the case where the inductors are seperate. The values shown should easily be ok. (In my limited experience with SEPIC that is!)

Ouroboros 5th August 2008 12:26 PM

Hmmm, I see that in a SEPIC converter (as opposed to a CUK converter), some people say that it is not wise to couple the two inductors on a single core, as the circuit then doesn't operate in the true SEPIC mode.

Fob 5th August 2008 06:19 PM

Hi Bootstrapper,
It is very brave to make SEPIC without current sensing. Change the controll to curent mode and then try to compensate whatever.

Claude Abraham 5th August 2008 07:42 PM

SEPIC is complex
It sounds like control loop instability. A SEPIC is a complex topology, and not trivial when it comes to compensation. At light load it operates in discontinuous mode, and should be stable. But, if it enters continuous mode, at heavier load current, stability becomes complicated.

Dr. Ridley on his site "Switching Power Magazine" has a good paper that covers the SEPIC issues. I'd recommend downloading, as it is free. The SEPIC in continuous mode has a small signal transfer function with 2 pairs of complex conjugate poles (4 poles in all), as well as 3 right half plane zeroes. The only way to compensate and achieve stability with 7 lagging singularities would be to limit the loop bandwidth to a frequency less than the upper complex pole pair, or lowest right half plane zero, whichever is *lower*. The end result is usually a converter with very limited speed. Transient response due to sudden changes in load or input will be impaired. With 4 poles and 3 right half plane zeroes, the total phase lag approaches 630 degrees!

I've designed close to 100 SMPS, and my converters are in millions of products worldwide. I have never used the SEPIC topology for reasons above. A good careful design using the SEPIC topology can be done. One simply must be careful. For up/down conversion sans isolation, I use the non-inverting buck-boost (NIBB) topolgy. It has 2 FETs and 2 diodes vs. 1 FET and 1 diode for the SEPIC. The efficiency of the NIBB is slightly less than that of the SEPIC, but the speed is much better. The NIBB in continuous mode has only 1 pair of complex conjugate poles, and 1 right half plane zero. Stability is assured by limiting the control loop BW to less than the right half plane zero frequency.

I hope this helps.

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