lossless clamping with current sense, how?

[zilog]

I have a push-pull smps with current sense transformers on the primary side, feedback using average current mode control. This all works fine, the problem is how to do the lossless clamping in a way that does not interfere with the current sensing.

Please dont complain about the ringing on the waveforms, this is just a veroboarded prototype. The probes are 1:10, so the current from ISNS is 10A/div.

I have tried the two ways of connection that is shown in this schematic: http://wintermute.csbnet.se/~zilog/s...uit_cursns.JPG and get the following waveforms for ISNS with them, http://wintermute.csbnet.se/~zilog/s...mp_schema2.JPG for the upper version of the circuit, and http://wintermute.csbnet.se/~zilog/s...mp_schema1.JPG for the bottom part of the circuit.

I feel that I want to use the bottom part of the circuit since this eases routing and transformer design, but it produces ugly waveforms. What is the proper way to do this?

[zilog]

I think I have sorted it out now - the current sense elements must not be included in the reset-winding-loop, thus is the top schematic the way to go. Too bad since this complicates layout and transformer winding..

[Eva]

The (one turn) primaries of the current transformers should be left in an high impedance state during reset, else they won't reset at all. This is obviously achieved by leaving them out of the clamping circuit, in series with the drains.

The question is: Why do you need a clamping circuit in the first place? I have made a few push-pull SMPS like this and spikes due to leakage inductance were never a major problem. In my class D car amplifier, the little SMPS has to handle 600W peak (50A) and the drain spikes at turn-off are still not tall enough to bring the 60V MOSFET into avalanche. There is nothing special about the transformer employed, it's a 32mm OD toroid with optimum and tight winding layout. I think that with a better transformer you could just avoid any clamping.

Anyway, the circuit won't benefit from all the advantages of average current mode (like great immunity to input voltage changes or precise current limiting) if you don't include the current downslope in the waveform. In these circumstances, peak current mode (with some slope compensation) should perform better.

[zilog]

Originally posted by Eva
The (one turn) primaries of the current transformers should be left in an high impedance state during reset, else they won't reset at all. This is obviously achieved by leaving them out of the clamping circuit, in series with the drains.

The question is: Why do you need a clamping circuit in the first place? I have made a few push-pull SMPS like this and spikes due to leakage inductance were never a major problem. In my class D car amplifier, the little SMPS has to handle 600W peak (50A) and the drain spikes at turn-off are still not tall enough to bring the 60V MOSFET into avalanche. There is nothing special about the transformer employed, it's a 32mm OD toroid with optimum and tight winding layout. I think that with a better transformer you could just avoid any clamping.

Anyway, the circuit won't benefit from all the advantages of average current mode (like great immunity to input voltage changes or precise current limiting) if you don't include the current downslope in the waveform. In these circumstances, peak current mode (with some slope compensation) should perform better.

Yeah, I made a mistake with the CT:s there. I have just assumed that the transformer would waste a lot of energy through the leakage inductance since I use peak currents of 130A on each primary, but maybe I can manage without the lossless scheme. And besides, my extremely lousy air-wired prototype has loads of leakage inductance, and almost nothing even takes a tiny bit out of the turn off-spike.. but maybe that wont be a problem using a proper PCB.

How much wattage can I assume the clamp resistors in RC-clamping need to handle if I were to route a proper 2-layer PCB with an ETD29-core for the main transformer? Its just that I really dont like wasting energy each cycle in RC-snubbers, my current clamping scheme should not waste energy unless the smps is loaded.

I currently use a current downslope synthesizer which assumes worst case, but this will be improved since the final curcuit will be implemented using a DSP which performs the control loop in software, and I think I should be able to adjust the downslope estimate according to input voltage and other parameters, maybe also be able to switch control loop on the fly depending on loading scenario etc.

The reason for wanting to use a DSP is that I am curious to whether this solution holds for another project I have in mind or not, not because it is needed for this project.

/Daniel

[Eva]

The purpose of the RC snubbers is not to dissipate the energy stored in primary-to-primary leakage inductance but to damp ringing and reduce EMI. Remember that averaged EMI tends to be proportional to the amount of ringing oscillation periods.

The push-pull circuit is self clamping by means of the coupling between primaries. The better the primaries are coupled one to another, the smaller the spikes become. These spikes only result in substantial dissipation when they are tall enough to produce avalanche.

I have never done push-pull with ETD cores, only with toroids because this allows for perfectly symmetrical primaries and secondaries. You will have to experiment with transformer winding techniques to achieve the lowest leakage inductance. For 130A peak you may have to use two or three ETD29, this is 1500W. In my 15V 125A SMPS I used two E42/21/20 for 1800W.

You should make an optimum prototype of the power section with double sided PCB, ground plane and tight loops in order to evaluate the spikes. The control section is usually fine even in breadboard.

I don't know if the DSP solution is really worth the effort. However, once you have a powerful CPU core, fast memory, fast A/D and hardware PWM you can do many interesting things to the waveforms. I'm currently entering that world with PIC16s but they have little power.

[zilog]

So this means that I can allow the ringing to be arbitrarily high in voltage, as long as I dont allow it to reach avalanche, and the ringing energy will find its way to the secondary side in due time?

Originally posted by Eva
I have never done push-pull with ETD cores, only with toroids because this allows for perfectly symmetrical primaries and secondaries. You will have to experiment with transformer winding techniques to achieve the lowest leakage inductance. For 130A peak you may have to use two or three ETD29, this is 1500W. In my 15V 125A SMPS I used two E42/21/20 for 1800W.

The circuit is only designed to withstand 150W average thermally, but will allow 115-130A peak before the cycle-by-cycle limit cuts in. The purpose (of this particular smps) is to feed a couple of class d-amps running from +-45V and potentially feeding 2 ohm speakers.

Originally posted by Eva
I don't know if the DSP solution is really worth the effort. However, once you have a powerful CPU core, fast memory, fast A/D and hardware PWM you can do many interesting things to the waveforms. I'm currently entering that world with PIC16s but they have little power. [/B]

I hope the ti tms320F28016 I will be trying is fast enough with its 3.75 Msamples/second 10-bit AD (will need to split that in 2 since I will measure both output voltage and input current in a round-robin fashion) to do both cycle-by-cycle limit, and ACMC-feedback on the current values. I also hope I can assemble some crude form of IDE/compiler for it without having to pay the 500$ the commercially available ones cost..

One of the gains I hope to get, is that I can choose to ignore parts of the waveforms since the current peaks should drop after the switches have turned off, also to be able to only have the pwm active in bursts when the load is low. Same with the voltage balancer that I will employ to the secondary side to keep the rails tracking even under reactive load.