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Old 2nd April 2008, 07:57 PM   #1
zilog is offline zilog  Sweden
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Default push-pull smps funny observation

I have an smps prototype using the schematic in http://wintermute.csbnet.se/~zilog/schemat.jpg

I observe the waveform below on ISNS_OUT, but its the same at ISNS, except the smooth downslope - http://wintermute.csbnet.se/~zilog/s...ynthesized.jpg

1 div is full on-time for one primary phase, 1 div is 20A current. Is it normal that when one primary stops conducting, the current in the other phase continues where the other one left off, but then again it all begins at zero? I would expect to see sawtooths that return to zero, or the same level atleast between each conduction interval.

I suspect this causes the smps to duty cycle-limit at 60% given high load.

EDIT: the smps uses Average Current Mode Control
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Old 2nd April 2008, 11:21 PM   #2
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It's pretty clear to me why 33 people didn't respond to this. Maybe if you make it legible, someone will help you.
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Old 3rd April 2008, 12:32 AM   #3
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loving the coffee stains on his brutalised schematic.

can't really say i can offer any advice on your problem.

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Old 3rd April 2008, 06:24 AM   #4
zilog is offline zilog  Sweden
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For some clarification, I have drawn a figure of how I think the waveforms should look like in a push-pull smps Click the image to open in full size.

"A" and "B" is the time primary 1 respectively primary 2 are switched on, "C" is the average level the current reaches at equilibrium.
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Old 3rd April 2008, 06:36 AM   #5
zilog is offline zilog  Sweden
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Got a random idea.

The output iductors are wound on a common core, could this phenomenon be caused by reversing the direction of one of the windings? I must check when I get the time.
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Old 3rd April 2008, 09:27 PM   #6
zilog is offline zilog  Sweden
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I tried reversing the direction of one of the windings on the output inductor - no observable change in anything. Then I disconnected the B+ return wires for the clamping capacitors/diodes - efficiency dropped like a stone, but the current waveforms all went normal, sawtooths starting on the same current level for both primary phases.

Is there any special magic I have missed when it comes to lossless clamping and A-CMC? I guess the clamping scheme messes with the primary side current waveforms, looks like the core goes into saturation at certain voltages, but at 0.2 volt higher input, it looks normal when the clamping is connected - guess it also affects the control loop in some way.

Isnt Eva here somewhere to spread wisdom?
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Old 3rd April 2008, 09:59 PM   #7
zilog is offline zilog  Sweden
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I rerouted the lossless clamping to go through the current sense transformers - suddenly the primary current waveforms became identical for both push pull-channels. 4 div == full on-time for one primary channel, i div vertical == 20A.

One problem remains however (for both directions of winding for the output inductor) - I get this output from my sense transformers (called ISNS in the schematic): Click the image to open in full size.

I feed the smps 15.1V from a very capable PSU, and I cannot get the full output voltage from the smps, what strangeness am I observing here? What could possibly cause the dI/dt of the output inductor to change so sharply?
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Old 5th April 2008, 04:28 PM   #8
zilog is offline zilog  Sweden
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I have now rewound the mutually coupled inductor using half the Bmax compared with the last one, still no change in behaviour.

One funny thing though - I now get this reading from the combined signal from the CT:s (ISNS) - Click the image to open in full size.

I dont think the reason for every second pulse to be higher is transformer saturation because the current doesnt rise exponentially towards the end of the on-period.

The main transformer has Ae = 125mm^2, 3 turns per primary, and each primary is turned on for a maximum of 9us, the input voltage is 15V at maximum which yields dB ~3900-4000G which should be fine.

Am I observing CT saturation?
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Old 6th April 2008, 04:19 PM   #9
zilog is offline zilog  Sweden
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I have now rewound the CTs using large 3F3 ferrites, the difference in peak current between the primaries is now almost gone, guess I miscounted the number of turns for the original CTs.

I do still have problems with getting high current from the smps, the controller gives 100% duty-cycle, still the output conducts current for maximum ~60% of the time, have a look at this picture: smps_output_and_input.jpg

It shows two traces: the voltage from the secondaries of the transformer, and the drain voltage of one of the primary switch transistors, low voltage means its conducting current.

It looks like it takes some time after the mosfets turn on until voltage is present at the input to the secondary rectifiers, If I look at the output from the current transformers I can also observe this behaviour as a current that initially rises fast (no voltage yet at the output of the transformer), and then changes slope halfway through the conduction cycle (now voltage becomes present on the transformer secondaries), see this picture: smps_curr_x_former.jpg

It seems to me like the main transformer "consumes" current to begin with, and until it has had a certain amount of energy, it wont function as a transformer. The core is of unknown ferrite, but it doesnt seem to go into saturation as it stays cold even at prolonged 150W power levels.

Could this have something to do with the transformer ferrite material? Should I try to get hold of some large gauge 3F3 just for a test?
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Old 6th April 2008, 11:08 PM   #10
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First thing fix those waveforms- they look just as sloppy as your schematic. They look horrible. Get rid of the ringing.

As far as those waveforms not being in sync. Measure across primary fet (as you have) and measure across pins 4-6 of xfmr. If the scope does not like it, measure fronm 4-5.

.
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