I could imagine a rectangular hole or recess in the board the cap goes in, just within the boundaries of the SMT pin pads, and the chip put on top of that. This would minimize stray fields and everything. I wouldn't be surprised to find something like this being done (and someone having one or more patents related to it despite it being obvious to me, though that's OT for this thread).
The book "High Speed Signal Design" shows this kind of thing, that a (sufficiently short) pulse along a trace will have its return current travel back right under it along the ground plane, as if the return current were only traveling through a shadow trace under the signal trace. I just found it, pp 189-190, "High-Speed current follows the path of least inductance." Thus it's good to keep conductors of both the "forward" and "return" currents close together, reducing the loop area as much as possible. As explained earlier in the book, putting a conductor closer to the groundplane also reduces generated EMI.
I recall DIP sockets with a regular 0.1uF leaded capacitor mounted diagonally between the corner pins (7 and 14, or 8 and 16). That's about as short as you can get without mounting the cap on top and soldering the leads to the chip pins.
And that's the WORSE way you can try to decouple an OpAmp... No manufacturer does that, always between each power rail and GROUND -that's where the load is connected too.
http://www.analog.com/static/imported-files/tutorials/MT-101.pdf
Oh dont we use digital in audio?
Benb
High Density Interconnect, is the way forwad for PCB design and high speed layout. The board is also the capacitor.
http://www.laocsmta.org/archive/Embedded_Capacitance_Presentation.pdf
http://www.ddmconsulting.com/Design_Guides/bcguide.pdf
http://ecadigitallibrary.com/pdf/CARTS06/5_9squ.pdf
Have a look at some of the stuff that is happening with PCB's these days, lots of fun stuff, you can even embedd 0201, 1005 chip components into the final build.
Welcome
The best way for SMD decoupling with std circuit boards is to via the power pins to the planes and to via the capacitor pins to the plane, no routes between the caps and the power pins. This gives the lowest impedance, of course you require planes, we often have up to 16, with multiple grounds, though HDI makes life a lot easier and cuts down on the number of planes required. We then have to decied which power plane pairs hould be nearest the chips (ie top layer of PCB) and which should be near the bottom, made more fun when you have double sided placement...
Oh and of course with standards such as 74 logic, there was always an exception, the 74LS76
Benb
High Density Interconnect, is the way forwad for PCB design and high speed layout. The board is also the capacitor.
http://www.laocsmta.org/archive/Embedded_Capacitance_Presentation.pdf
http://www.ddmconsulting.com/Design_Guides/bcguide.pdf
http://ecadigitallibrary.com/pdf/CARTS06/5_9squ.pdf
Have a look at some of the stuff that is happening with PCB's these days, lots of fun stuff, you can even embedd 0201, 1005 chip components into the final build.
Welcome
The best way for SMD decoupling with std circuit boards is to via the power pins to the planes and to via the capacitor pins to the plane, no routes between the caps and the power pins. This gives the lowest impedance, of course you require planes, we often have up to 16, with multiple grounds, though HDI makes life a lot easier and cuts down on the number of planes required. We then have to decied which power plane pairs hould be nearest the chips (ie top layer of PCB) and which should be near the bottom, made more fun when you have double sided placement...
Oh and of course with standards such as 74 logic, there was always an exception, the 74LS76
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Wnet to an engineering day that Wurth ran recently, some of the stuff is getting, was amazed at some of the dev work they are playing with. One of the coolest that will be with us soon, is milling a cavity in the PCB and wire bonding the actual chips into the PCB, then sealing it in with the next layers. The prolifaration of mobile devices and the demand for more computing power, less energy used size and cost is driving the technology.
Flexi rigid are my favorites at the moment, a digital/analogue system could be built where the various parts could be seperated for noise, and with the flexi limbs I2S or similar (instead of SPDIF) could be used for the digital, without the signal integrity problems of going off board, and it could all be folded up neatly in a box. Done somthing similar, but its covered by NDA's etc. A similar idea is discussed here:
Printed Circuit Design & Fab Magazine Online
Flexi rigid are my favorites at the moment, a digital/analogue system could be built where the various parts could be seperated for noise, and with the flexi limbs I2S or similar (instead of SPDIF) could be used for the digital, without the signal integrity problems of going off board, and it could all be folded up neatly in a box. Done somthing similar, but its covered by NDA's etc. A similar idea is discussed here:
Printed Circuit Design & Fab Magazine Online
Scary close layer spacing, high dielectric, I'm all in favor but isn't it possible audio performance may actually take a hit in long term reliability and piezo electric effects?
Thanks
-Antonio
These sort of boards are for high speed digital. Personal preference and a scheme we follow where possible at work, is a digital board and an analogue board, with isolation. This is getting harder to achieve as things shrink down, and as always cost.
High dialectric layers cause there own problems, as speed of proagation goes down with increased dialectric constant. This reduces the effective area of the capacitive layers! This is only a concern at realy high speeds, but with DDR3 memory becoming standard and high speed FPGA's its standard these days. A friend of mine is doing a board where some signals can only be routed a max distance of 1". We often work on an area 20mm x 10mm zoomed to fill a 23" wide screen monitor.
I will have a look around and see if any research has been done on noise induced by piezo effects in HDI construction PCB's.
The chips embeded within PCB's are not wire bonded, but bump bonded, like tiny BGA's.
Tha advantage of having digital and analogue boars is so the construction of each can be optimised. Digital, high speed 10-16 layers HDI, thin copper (1/2oz and less), fine line design (0.004"/0.004" track and gap). Analoge (and power) less layers 4-8, heavier copper (2oz), heavier traces (0.010-0.100).
High dialectric layers cause there own problems, as speed of proagation goes down with increased dialectric constant. This reduces the effective area of the capacitive layers! This is only a concern at realy high speeds, but with DDR3 memory becoming standard and high speed FPGA's its standard these days. A friend of mine is doing a board where some signals can only be routed a max distance of 1". We often work on an area 20mm x 10mm zoomed to fill a 23" wide screen monitor.
I will have a look around and see if any research has been done on noise induced by piezo effects in HDI construction PCB's.
The chips embeded within PCB's are not wire bonded, but bump bonded, like tiny BGA's.
Tha advantage of having digital and analogue boars is so the construction of each can be optimised. Digital, high speed 10-16 layers HDI, thin copper (1/2oz and less), fine line design (0.004"/0.004" track and gap). Analoge (and power) less layers 4-8, heavier copper (2oz), heavier traces (0.010-0.100).
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Marce
Understand.
I was thinking along the lines of employing all th latest techniques to provide the best decoupling or by-pass (theorectically anyway as I could never justify or afford the price of the boads discussed), but you remind me that the best over the audio range (including all frequency just beyond the crossover) may not be the same as those intended to extend into the giga hz range.
Thanks
-Antonio
Understand.
I was thinking along the lines of employing all th latest techniques to provide the best decoupling or by-pass (theorectically anyway as I could never justify or afford the price of the boads discussed), but you remind me that the best over the audio range (including all frequency just beyond the crossover) may not be the same as those intended to extend into the giga hz range.
Thanks
-Antonio
Design of VDD bypassing for PowerAmplifier
Suppose we have a number of 10,000 uF caps, about an inch apart,
wired together with twisted_pair for minimum area and thus minimum
inductance.
Assume 10nanoHenry for the wiring between caps, the L*C product
is 10^-8 Henry * 0.01Farad or 10^-10. We square_root that and invert,
finding the radians/sec is 100,000 and the resonant freq is 16,000Hertz.
Definitely able to cause coloration. Note that bigger caps will also use
bigger wiring loops, and the resonant freq drops more and more.
So lets work with the 10,000UF and 10nanoHenry.
How to dampen that?
"wikipedia damping ratio" is helpful, with plots.
And "zeta" = 1/(2*Q)
At zeta of 0.7, we have no overshoot, {figure below bouncing spring}
after a surge of charge is pulled from the reservior capacitors.
The Q would be 1/2*zeta = 1/2*0.7 = 1.4, telling us the ratio
of inductive_impedance/dampening_resistor {also Xc/R}.
Let's just aim for Q=1, meaning Zl = Zc = Resistor. Simple. I like simple.
Xl=Xc at the ringing freqency; Xl = radians/sec * L = 100,000 * 10^-8
Xl = 10^5 * 10^-8 = 10^-3 = 1 milliOhm.
And an inch of #20 wire provides 1 milliOhm.
Thus, putting aside any use of ESR and solder_resistance and
skin_effect etc etc, we can use the wires to provide the dampening.
SUMMARY: aim for Q=1 (easy to remember), and aim for
1 inch or more of small wires between the caps to be resistive/lossy,
and thus reduce the coloration. In other words, huge wires are not
good for coloration. Surprise?
tank
#20 AWG solid wire is 10 ohms/thousand feet,
10 milliOhm/foot, 1milliOhm/1_inch.
Can we bring the 10,000 uF caps right up to the output transistors?
10nH is approx 20mm of wire; twisting VDD/GND together
will reduce the 10nH of VDD and 10nH of GND back to 10nH total,
and we now have 2 milliOhm of dampening.
We know the mechanical engineers design different brands of
capacitors differently, hence the internal inductance will vary.
Experiment with other caps right at the output transistor
collector_GND nodes,
L=10nH C=10,000uF Fring=16KHz Rdamp=1mOhm
L=10nH C=100uF Fring=160KHz Rdamp=10mOhm
L=10nH C=1uF Fring=1,600KHz Rdamp=100milliOhm
At L=100nH, freqs drop by 1/sqrt(10), and Rdamp increases by sqrt(10)
At L=1,000uH, freqs drop by 1/10, and Rdamp increases by 10X.
Thus with longer wiring, the dampening Rs should be larger in value.
How much power will discrete resistors dissipate?
Power = I*I*R, thus at 5amps RMS and 1milliOhm, the wire
dissipates 25 milliWatts---in the wire.
Unless we have an unstable amplifier, there will be little
energy at 160KHz or at 1,600KHz, and similar small dissipation
will occur in any discrete SMT dampening resistors.
I think. I have not done the math on this. Who wants to?
tank (All mistakes are mine)
Suppose we have a number of 10,000 uF caps, about an inch apart,
wired together with twisted_pair for minimum area and thus minimum
inductance.
Assume 10nanoHenry for the wiring between caps, the L*C product
is 10^-8 Henry * 0.01Farad or 10^-10. We square_root that and invert,
finding the radians/sec is 100,000 and the resonant freq is 16,000Hertz.
Definitely able to cause coloration. Note that bigger caps will also use
bigger wiring loops, and the resonant freq drops more and more.
So lets work with the 10,000UF and 10nanoHenry.
How to dampen that?
"wikipedia damping ratio" is helpful, with plots.
And "zeta" = 1/(2*Q)
At zeta of 0.7, we have no overshoot, {figure below bouncing spring}
after a surge of charge is pulled from the reservior capacitors.
The Q would be 1/2*zeta = 1/2*0.7 = 1.4, telling us the ratio
of inductive_impedance/dampening_resistor {also Xc/R}.
Let's just aim for Q=1, meaning Zl = Zc = Resistor. Simple. I like simple.
Xl=Xc at the ringing freqency; Xl = radians/sec * L = 100,000 * 10^-8
Xl = 10^5 * 10^-8 = 10^-3 = 1 milliOhm.
And an inch of #20 wire provides 1 milliOhm.
Thus, putting aside any use of ESR and solder_resistance and
skin_effect etc etc, we can use the wires to provide the dampening.
SUMMARY: aim for Q=1 (easy to remember), and aim for
1 inch or more of small wires between the caps to be resistive/lossy,
and thus reduce the coloration. In other words, huge wires are not
good for coloration. Surprise?
tank
#20 AWG solid wire is 10 ohms/thousand feet,
10 milliOhm/foot, 1milliOhm/1_inch.
Can we bring the 10,000 uF caps right up to the output transistors?
10nH is approx 20mm of wire; twisting VDD/GND together
will reduce the 10nH of VDD and 10nH of GND back to 10nH total,
and we now have 2 milliOhm of dampening.
We know the mechanical engineers design different brands of
capacitors differently, hence the internal inductance will vary.
Experiment with other caps right at the output transistor
collector_GND nodes,
L=10nH C=10,000uF Fring=16KHz Rdamp=1mOhm
L=10nH C=100uF Fring=160KHz Rdamp=10mOhm
L=10nH C=1uF Fring=1,600KHz Rdamp=100milliOhm
At L=100nH, freqs drop by 1/sqrt(10), and Rdamp increases by sqrt(10)
At L=1,000uH, freqs drop by 1/10, and Rdamp increases by 10X.
Thus with longer wiring, the dampening Rs should be larger in value.
How much power will discrete resistors dissipate?
Power = I*I*R, thus at 5amps RMS and 1milliOhm, the wire
dissipates 25 milliWatts---in the wire.
Unless we have an unstable amplifier, there will be little
energy at 160KHz or at 1,600KHz, and similar small dissipation
will occur in any discrete SMT dampening resistors.
I think. I have not done the math on this. Who wants to?
tank (All mistakes are mine)
Tank,
Cool! I can hardly wait to go over your last post and maybe also see how it ties in with the decoupling cap stuff I did earlier. Right now I'm still trying to beat a deadline for completion of some mandatory training for work. Bummer. But I hope to be able to get back to this as soon as that's finished, maybe by tomorrow.
Cheers,
Tom
Cool! I can hardly wait to go over your last post and maybe also see how it ties in with the decoupling cap stuff I did earlier. Right now I'm still trying to beat a deadline for completion of some mandatory training for work. Bummer. But I hope to be able to get back to this as soon as that's finished, maybe by tomorrow.
Cheers,
Tom
re: Cb = 50/pi*fc equation for op amp primary power supply bypass cap
Graeme contends that the 1-ohm guideline almost always assures stability, therefore
ZCb = 1/2*pi*f*Cb = 1 ohm
gives
Cb = 1/2*pi*f
Selecting f = fc/100 gives the general equation Cb = 50/pi*fc
My understanding is he advocates f << fc to make analysis easier, as it negates much of the parasitics.
Graeme contends that the 1-ohm guideline almost always assures stability, therefore
ZCb = 1/2*pi*f*Cb = 1 ohm
gives
Cb = 1/2*pi*f
Selecting f = fc/100 gives the general equation Cb = 50/pi*fc
My understanding is he advocates f << fc to make analysis easier, as it negates much of the parasitics.
Excellent thread!
I soldered on a matrix board a line level active crossover with 6 x OPA627 opamps tightly lined up together supplied by LM317/337 regulators with 16AWG wires for both rails and ground in a short distance (less than 100mm). I had 3 x 2,200uF after the LM317/337, and 4 x 100uF electrolytic caps and 4 x 0.1uF MKP caps soldered directly on the 16AWG wires close to the opamp supply pins.
I EXPECTED resonances on the rails at some higher frequencies.
However, my old oscillioscope with limited resolution (I can see 1mV ripples up to 10MHz) did not show any resonances from 20Hz to 10MHz. All I saw was only a flat line.
I then connected a CD player to the active crossover and played some music. It appeared that this did not trigger any resonances on the rails, as what I saw on the oscillioscope was still a flat line.
Does this mean that parallelling capacitors in this particular case happened to work well for me? or my measurement equipment is not good enough?
Regards,
Bill
I soldered on a matrix board a line level active crossover with 6 x OPA627 opamps tightly lined up together supplied by LM317/337 regulators with 16AWG wires for both rails and ground in a short distance (less than 100mm). I had 3 x 2,200uF after the LM317/337, and 4 x 100uF electrolytic caps and 4 x 0.1uF MKP caps soldered directly on the 16AWG wires close to the opamp supply pins.
I EXPECTED resonances on the rails at some higher frequencies.
However, my old oscillioscope with limited resolution (I can see 1mV ripples up to 10MHz) did not show any resonances from 20Hz to 10MHz. All I saw was only a flat line.
I then connected a CD player to the active crossover and played some music. It appeared that this did not trigger any resonances on the rails, as what I saw on the oscillioscope was still a flat line.
Does this mean that parallelling capacitors in this particular case happened to work well for me? or my measurement equipment is not good enough?
Regards,
Bill
Yes, 10 MHz is too low to declare that there is not a problem. Sometimes that's around the point where the impedance seen by the power supply pins is just starting to increase rapidly. Someone on another thread somewhere mentioned, a day or two ago, that they had a strong oscillation at 300 MHz.
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