Tank,
Thanks. So far so good. But...
At least in my case, the worry is now more about supporting the production of transients with extreme accuracy in the time domain, rather than voltage-drop issues (except as they relate to supplying transient current demands).
Lately, in order to get a feel for the trade-space involved, and also to end up with something that can be applied, I've been trying to approach it quantitatively, for purposes of both analysis and synthesis, by trying to re-derive the methods for calculating "what real capacitors, with what real PCB traces or wires, WOULD be sufficient for providing a specific transient current, given a demanded current level and the risetime needed?". (And by re-derive, I mean doing what others have already done in other contexts. I never delved into it, before this, and also haven't found any material on doing it in this context, or for anything with comparable transient currents.)
We actually don't want to limit ourselves to 20 kHz, either. I think that 250 kHz is a reasonable frequency response upper limit, for an audio system, if we want to preclude creating too many artifacts where it matters.
So that's a worst-case risetime of about 1.273 μs, zero to rail.
That could be interesting, with a 60V rail and a 4 Ohm load, especially if the allowable rail voltage disturbance is very small.
Tiny capacitors won't do it. It's in the 100s of μF.
Those are larger so then the trace lengths have to be longer.
And the traces handle large-ish currents so they can't be overly narrow.
And the capacitors' intrinsic inductances are also relatively large, now.
Accurate-as-possible timing of the amplitude and the phase angle of the delivered current are critical.
Due mainly to parasitic inductances, it looks like it can't be done with any single cap and will require paralleling multiple smaller caps as well as all of their connections to the decoupling points.
We'd like to be able to implement any resulting methods on home-made two-sided or one-sided PCBs, or else show that it can't be done, and want to be able to quantify the limits of various available DIY construction types and components, in this context.
Interested yet?
I started on this in earnest in posts 221 and 224, did some more in 252, which led me to do posts 310-314 and 319. And then I got busy and/or distracted and here we are.
Regards,
Tom
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I've read the pages of data here saying parralled film caps create instability and mulitiple power suuply resonances. I appeciate your knowledge and arguments , but I also hear an improvement in my system when I add 10uf and 0.01uf film caps across the power supply electrolytics - so whats happening. Am i attracted to barely stable power supplies?
Every case is unique. I could see a 10 μF film cap as possibly having some good effect.
Can you hear a difference when just the 0.01 uF cap is added or removed?
And I think that actually it is possible that some might prefer the sound of a marginally-stable or a somewhat-resonant circuit. A lot might depend on the details of the circuit. So it's difficult to speculate. It could even be alleviating some other problem, and actually making it cleaner.
The "rule" is to not do it indiscriminately, I think. But that doesn't mean that you can't get lucky.
Can you hear a difference when just the 0.01 uF cap is added or removed?
And I think that actually it is possible that some might prefer the sound of a marginally-stable or a somewhat-resonant circuit. A lot might depend on the details of the circuit. So it's difficult to speculate. It could even be alleviating some other problem, and actually making it cleaner.
The "rule" is to not do it indiscriminately, I think. But that doesn't mean that you can't get lucky.
Does no one else think that this stuff is worth thinking about?
Almost all of the power amplifier layouts that I have ever seen on diyaudio look like they would be slew rate limited by their decoupling capacitors, under at least some of their normal operating conditions.
That means transient distortion, which doesn't usually show up when you measure THD.
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VDD sag: dV/dT = I/C thus 1uF&1Amp -> 1volt/uSec
5uF and 5Amps -> 1 volt/uSec
Yes, I skipped over the serious sag in VDD,
if only small (5uF, 50uF, 500uF) caps are used as the
reservior.
In a previous life, examing VDD_bypassing for precision
OpAmp settling, I was appalled at the implications
(meaning I've ignored major error sources for signal processing)
of the collapse in PowerSupplyRejection above about
100Hertz, in most OpAmps.
Many OpAmps have PSR of approx 1 (ONE) at high frequencies(100KHz),
where ONE means the VDD trash glides thru the various
internal transistors (FETS in many cases) and fully appears on
the output pin. Sometimes you'll get 6dB (50%) drop,
but that just means the HighFreq trash on the shared/common
+V/-V rails from left channel treble energy surges
will appear with only 50% less treble energy on the right channel.
Kinda kills the imaging, I suppose.
I was examining the challenges of feeding accurate fast-changing
signals from an analog multiplexor (such as a space-craft telemetry
system monitoring heart-beat, blood-pressure, fuel-cell output,
battery temperature, heat-shield temperature, hydrazine pressure)
into a 10-bit Analog2DigitalConverter, with 100,000 samples per
second into the ADC. Given 5 volt FullScale into ADC, a single
quanta would be 5/2^10 or 5/1024 or 4.9 milliVolts.
Thus the telemetry VDD needed to be QUIET within 5 milliVolts,
or even better, because some of the channels were providing
substantial amplification (such as the heart-monitor circuits)
before the analog multiplexor.
Anyway, addressing the dampening of VDD, over wide range
of audio and ultrasonic frequencies, seems the correct approach.
Assuming 100 nanoHenry inductance (10 nH is difficult to achieve,
unless Ground/VDD planes are used), we have the following
inductive impedances at various frequencies of interest
{ I memorized 1uH and 1Megacycle as j6.3 ohms, as a kid}
10MHz J6.3 ohm
1MHz 0.63 ohm
100KHz 0.063 ohm
10KHz 0.0063 ohm
1KHz 0.00063 ohm [ approximately 1 square of PCB foil ]
Plain wires are about 1nH/millimeter (with a mild dependence
on length/radius, but I ignore it), thus 100 millimeters (4 inches)
is 100 nanoHenries. FOUR INCHES between Caps and Transistors.
However, twisted pairs are your friend, tighly twisted, but
I have no tip-of-tongue rules for that. And PCBs with opposite
layers being GND and rail, are good. At least use the twisted pairs.
Note the dampening resistive values needed.
At 1KHz, the wire should provide 0.00063 ohm.
At 10KHz, a lossy ceramic.....might work. But it might get hot and fracture
as it absorbed treble transient energy. The solder, being very resistive,
may be the primary dampening agent in many amplifiers.
We are definitely in the region where those magic parasitics
do matter....but the solder? as primary dampener?
wow
tank
5uF and 5Amps -> 1 volt/uSec
Yes, I skipped over the serious sag in VDD,
if only small (5uF, 50uF, 500uF) caps are used as the
reservior.
In a previous life, examing VDD_bypassing for precision
OpAmp settling, I was appalled at the implications
(meaning I've ignored major error sources for signal processing)
of the collapse in PowerSupplyRejection above about
100Hertz, in most OpAmps.
Many OpAmps have PSR of approx 1 (ONE) at high frequencies(100KHz),
where ONE means the VDD trash glides thru the various
internal transistors (FETS in many cases) and fully appears on
the output pin. Sometimes you'll get 6dB (50%) drop,
but that just means the HighFreq trash on the shared/common
+V/-V rails from left channel treble energy surges
will appear with only 50% less treble energy on the right channel.
Kinda kills the imaging, I suppose.
I was examining the challenges of feeding accurate fast-changing
signals from an analog multiplexor (such as a space-craft telemetry
system monitoring heart-beat, blood-pressure, fuel-cell output,
battery temperature, heat-shield temperature, hydrazine pressure)
into a 10-bit Analog2DigitalConverter, with 100,000 samples per
second into the ADC. Given 5 volt FullScale into ADC, a single
quanta would be 5/2^10 or 5/1024 or 4.9 milliVolts.
Thus the telemetry VDD needed to be QUIET within 5 milliVolts,
or even better, because some of the channels were providing
substantial amplification (such as the heart-monitor circuits)
before the analog multiplexor.
Anyway, addressing the dampening of VDD, over wide range
of audio and ultrasonic frequencies, seems the correct approach.
Assuming 100 nanoHenry inductance (10 nH is difficult to achieve,
unless Ground/VDD planes are used), we have the following
inductive impedances at various frequencies of interest
{ I memorized 1uH and 1Megacycle as j6.3 ohms, as a kid}
10MHz J6.3 ohm
1MHz 0.63 ohm
100KHz 0.063 ohm
10KHz 0.0063 ohm
1KHz 0.00063 ohm [ approximately 1 square of PCB foil ]
Plain wires are about 1nH/millimeter (with a mild dependence
on length/radius, but I ignore it), thus 100 millimeters (4 inches)
is 100 nanoHenries. FOUR INCHES between Caps and Transistors.
However, twisted pairs are your friend, tighly twisted, but
I have no tip-of-tongue rules for that. And PCBs with opposite
layers being GND and rail, are good. At least use the twisted pairs.
Note the dampening resistive values needed.
At 1KHz, the wire should provide 0.00063 ohm.
At 10KHz, a lossy ceramic.....might work. But it might get hot and fracture
as it absorbed treble transient energy. The solder, being very resistive,
may be the primary dampening agent in many amplifiers.
We are definitely in the region where those magic parasitics
do matter....but the solder? as primary dampener?
wow
tank
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useful twisted-pair inductance web-link
A 2mm diameter wire, with 1mm insulation thickness around each wire,
thus center-center spacing of [ 1mm radius, 1mm insul, 1mm insul, 1mm radius]--->4mm, has inductance of 5 nanoHenry/centimeter.
Four inches of wire (10cm) would be 50 nanoHenry.
Impedance Calculators - Mantaro Product Development Services
For fun, I checked out the coaxial cable inductance (same web page),
and standard SOLID_CENTER, SOLID_SHIELD coax is 3nH/cm.
(1mm center, 4.7mm outer diameter)
And for much more fun, I used the "microstrip impedance calculator"
(same web page) with dimensions in millimeters:
4.5mm wide, 0.035mm thick (standard foil), with 1.5mm dielectric
thickness.
Inductance is only 1.8 nanoHenry / centimeter.
[unfortunately the formula blows up for interestingly wide widths]
tank
A 2mm diameter wire, with 1mm insulation thickness around each wire,
thus center-center spacing of [ 1mm radius, 1mm insul, 1mm insul, 1mm radius]--->4mm, has inductance of 5 nanoHenry/centimeter.
Four inches of wire (10cm) would be 50 nanoHenry.
Impedance Calculators - Mantaro Product Development Services
For fun, I checked out the coaxial cable inductance (same web page),
and standard SOLID_CENTER, SOLID_SHIELD coax is 3nH/cm.
(1mm center, 4.7mm outer diameter)
And for much more fun, I used the "microstrip impedance calculator"
(same web page) with dimensions in millimeters:
4.5mm wide, 0.035mm thick (standard foil), with 1.5mm dielectric
thickness.
Inductance is only 1.8 nanoHenry / centimeter.
[unfortunately the formula blows up for interestingly wide widths]
tank
Yes, and inductance of the connections for the decoupling capacitors can be a killer, especially as the caps get larger.
I am really starting to think that, sometimes, maybe even often, the only way to achieve a low-enough inductance for decoupling (and a low-enough impedance in general), as seen by a power output stage active load, and ALSO achieve a practical (i.e. implementable) physical placement and connection scheme for the decoupling caps, will be to use multiple smaller parallel caps, each with their own separate parallel connections to the points of decoupling.
But, at that point, maybe we should just "go all the way" and use multiple parallel conductors for each power and ground rail, too, everywhere after the first smoothing cap in the PSU.
That's all assuming the use of typical DIY construction techniques, i.e. a PCB with one or two sides with copper, or point-to-point wiring. But I STILL also think that it would be quite simple to use multiple pieces of PCB and fabricate a mutlilayer board assembly by hand, at home, even though it would require some workarounds, like large access holes to be able to solder on an inner layer, and vias would have to be hand-made, i.e. with a short wire inserted and soldered on both ends, et al.
Multiple layers would certainly make layout MUCH easier, especially because ground and power planes could be available basically everywhere. (And if we started with extremely-thin PCB laminates, we might even get some decent amount of high-frequency capacitance between layers.)
I still keep thinking back to the LM3886 chipamp's decoupling capacitor placement and connection problems. The pin-out basically just sucks, for that, especially for a one- or two-sided PCB. Pardon my Francais.
Here: http://www.ti.com/lit/ds/symlink/lm3886.pdf
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just n idea...
suppose we had a thin multilayer-cap of comparable high capacitance with the mechanical length of an ic and a width of an ic. The cap would be connectible on both sides along the full length of it. We now could stuck this cap directly under the ic and get the shortest possible connection. Ic manufacturers could even manufacture and supplie a ready made "sandwich" like this.
What do you thinck? Would possible resulting strayfields pose problems that could not be tackled?
suppose we had a thin multilayer-cap of comparable high capacitance with the mechanical length of an ic and a width of an ic. The cap would be connectible on both sides along the full length of it. We now could stuck this cap directly under the ic and get the shortest possible connection. Ic manufacturers could even manufacture and supplie a ready made "sandwich" like this.
What do you thinck? Would possible resulting strayfields pose problems that could not be tackled?
You can get those sort of decouplers for PTH DIP components, but when you move to SMD, that where the problems arise. The added problem is through hole components are in decline especially IC's, and SMD while it can be done on two layers, it is always a compromise.
As for two layer boards, they use to be equal 50-50 with multilayer, the split for 2010 for worldwide PCB production was 60% multilayer 11% two layer, the rest was made up of flexis, flexi-rigid, IC substrates and CEM.
And another amazing fact 6 billion passive components are placed on PCB's every day...
As for two layer boards, they use to be equal 50-50 with multilayer, the split for 2010 for worldwide PCB production was 60% multilayer 11% two layer, the rest was made up of flexis, flexi-rigid, IC substrates and CEM.
And another amazing fact 6 billion passive components are placed on PCB's every day...
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