That is another area where HDI PCb design is a winner, with the right layer stakup and blind and burried microvias you can minimise the loop area of the vias through the board.
My preference would be top layer power, second layer power, 0201 capacitors mounted between the balls aof the BGA device:
My preference would be top layer power, second layer power, 0201 capacitors mounted between the balls aof the BGA device:
Electrons like embedded 0201s too. 
I imagine, however, it'll be some time before HDI falls to a comfortably DIY accessible price point---if it weren't for Gold Phoenix a process with basic 10 mil DRCs would still be kind of steep. One can get some of the benefits in DIY on the smaller uSMDs, but the pick and place isn't exactly the easiest. Besides, I eat out of my toaster oven so, somehow, hooking it up to a microcontroller for use in reflow isn't really a priority.
All the higher end design techniques do transfer meaningfully over to audio, though. If we leave aside DACs with 20-100MHz clocks and DSPs with cores approaching 200MHz and just look at the analog side of things I, personally, would say entry level design to minimize susceptibility to layout issues and parasitics is a 10 or 20 mil DRC, two layer, surface mount board with op amps. That usually means 8-SOICs with Vcc, Vee, and ground pours and ground referenced regulators---you hope the part's operating in class A but without some careful supply measurements you never really know when it might flip in to class B. So all three pours need to come to the package with at least two caps (Vcc to ground, ground to Vee, typically 0805 to handle the supplies) with minimal supply noise coupling into the op amp's summing junction. Usually the best you can do is to pour into two or three of the cap terminals an run a few hundred mils of trace with a couple vias. Figure a nH or two per bond wire, package, pin, and via plus nH or so in each cap and five or more nH in the trace and the best case supply inductance is something not much below 20nH. That's two ohms at 100MHz.
This arguably crazy for a 20kHz signal but the reality of Miller compensated voltage mode feedback is a 20+MHz gain bandwidth product is required to get good linearity at 20kHz. In the case of a composite amp---just about every power amplifier in existence, in other words---the output devices have to be faster than the control loop for stability. So I typically end up working with parts having GBPs in the range of 75 to 200MHz. One can desensitize the system by lowpassing the feedback loops above the audio range. However, the parts will still amplify any internal problems up to their GBP. It doesn't take all that much of a high frequency wobble to consume a significant fraction of the control loop's slew rate, moving the part towards open loop. PSRR 's usually not so good in the tens of MHz either.
So I think there's a case for trying to do nice tight supply layouts. I don't know how much it actually matters in the end, having never deliberately done a layout of degraded quality and then taken A/B measurements to compare it to a better one. But I have a suspicion a significant portion of reported variability in DIY results with audio electronics is due to variations in point to point wiring, breadboarding, and PCB layout style.
I imagine, however, it'll be some time before HDI falls to a comfortably DIY accessible price point---if it weren't for Gold Phoenix a process with basic 10 mil DRCs would still be kind of steep. One can get some of the benefits in DIY on the smaller uSMDs, but the pick and place isn't exactly the easiest. Besides, I eat out of my toaster oven so, somehow, hooking it up to a microcontroller for use in reflow isn't really a priority.All the higher end design techniques do transfer meaningfully over to audio, though. If we leave aside DACs with 20-100MHz clocks and DSPs with cores approaching 200MHz and just look at the analog side of things I, personally, would say entry level design to minimize susceptibility to layout issues and parasitics is a 10 or 20 mil DRC, two layer, surface mount board with op amps. That usually means 8-SOICs with Vcc, Vee, and ground pours and ground referenced regulators---you hope the part's operating in class A but without some careful supply measurements you never really know when it might flip in to class B. So all three pours need to come to the package with at least two caps (Vcc to ground, ground to Vee, typically 0805 to handle the supplies) with minimal supply noise coupling into the op amp's summing junction. Usually the best you can do is to pour into two or three of the cap terminals an run a few hundred mils of trace with a couple vias. Figure a nH or two per bond wire, package, pin, and via plus nH or so in each cap and five or more nH in the trace and the best case supply inductance is something not much below 20nH. That's two ohms at 100MHz.
This arguably crazy for a 20kHz signal but the reality of Miller compensated voltage mode feedback is a 20+MHz gain bandwidth product is required to get good linearity at 20kHz. In the case of a composite amp---just about every power amplifier in existence, in other words---the output devices have to be faster than the control loop for stability. So I typically end up working with parts having GBPs in the range of 75 to 200MHz. One can desensitize the system by lowpassing the feedback loops above the audio range. However, the parts will still amplify any internal problems up to their GBP. It doesn't take all that much of a high frequency wobble to consume a significant fraction of the control loop's slew rate, moving the part towards open loop. PSRR 's usually not so good in the tens of MHz either.
So I think there's a case for trying to do nice tight supply layouts. I don't know how much it actually matters in the end, having never deliberately done a layout of degraded quality and then taken A/B measurements to compare it to a better one. But I have a suspicion a significant portion of reported variability in DIY results with audio electronics is due to variations in point to point wiring, breadboarding, and PCB layout style.
Thanks for that link. Good stuff.
No? According to Ott's book, the inductance WOULD be reduced by paralleling, as long as the parallel caps AND their leads and/or traces are not allowed to share mutual inductance.
So if each of the pairs of leads (or traces) is kept separate from the others (or the currents take separate-enough paths in power and ground planes) until reaching the two points across which the decoupling is needed, then the inductance should be lowered in the same way that resistance is lowered by paralleling resistors. ESR would also be lowered. And capacitance would be increased. Win/win/win.
I'm still not sure it's practical, or even necessary. But PLEASE NOTE that I was trying to think in terms of decoupling that is meant to be able to supply the needed (and sometimes large) transient currents for audio music signal transients, not decoupling to avoid high frequency problems, per se. It could be 200 uF or more, to meet a worst-case requirement to go from 0 to 10 Amps in 2 usec into 4 Ohms, for example.
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X2Ys are a subset of IDCs. X2Y's mounted inductance ratings pretty well covers it. AVX's LICC material touches on the same field theory as well. If one can get a meaningful ESL inductance from antiparalleling typical 'lytic cans that would be interesting. And surprising, as standard massively antiparallel 'lytic end terminations are on the order of 10nH and carefully built ones in moderate aspect ratio caps around 2nH (Nichicon S8, for example).
Obviously, the numbers here vary for different scenarios and one needs to identify the corners of the design space of interest. I'm sure someone will decide they want to build a power supply for a 140dB KISS concert using ESLs.
There's a line of an argument it'd be better to not have the amp follow the DAC's sync wiggles, which happens to reduces the slew rate requirement. Personally I find lowpass filtering the sync blurring from the FIRs is adding insult to injury---one gets a certain amount of lowpass from the tweeter's mechanical interia anyway---but others would argue a more relaxed high frequency response sounds less harsh and is therefore preferable.
X2Y's mounted inductance ratings pretty well covers it. AVX's LICC material touches on the same field theory as well. If one can get a meaningful ESL inductance from antiparalleling typical 'lytic cans that would be interesting. And surprising, as standard massively antiparallel 'lytic end terminations are on the order of 10nH and carefully built ones in moderate aspect ratio caps around 2nH (Nichicon S8, for example).Look at a DAC output with an oscope sometime. On a hard transient like a snare the FIR oversampling filter's sync response produces sizeable ringback; a realistic worst case is something around 70% of the DAC's swing between samples. At 44.1 that's about 125mV/us for a typical 2V DAC. Follow it with a typical 30dBish gain power amp and you get about 4V/us into a typical 4 ohmish speaker, or 1A/us. This implies a peak SPL in the 115 to 120dB range which is a bit unrealistic for home audio---90 to 100dB is more typical, implying more like 100mA/us---but people do crank it that hard. With point source speakers supply induced distortion in the amp's likely swamped by the driver distortion at 110+dB. But if one has a line array and a determination to destroy one's hearing...
Obviously, the numbers here vary for different scenarios and one needs to identify the corners of the design space of interest. I'm sure someone will decide they want to build a power supply for a 140dB KISS concert using ESLs.
There's a line of an argument it'd be better to not have the amp follow the DAC's sync wiggles, which happens to reduces the slew rate requirement. Personally I find lowpass filtering the sync blurring from the FIRs is adding insult to injury---one gets a certain amount of lowpass from the tweeter's mechanical interia anyway---but others would argue a more relaxed high frequency response sounds less harsh and is therefore preferable.
Glad it was helpful.
The point was that the decoupling caps are supposed to supply the leading edge of the transient. And the bulk PSU caps supply the rest and recharge the decoupling caps. This is about sizing the decoupling caps and the inductance that connects their internals through the power and ground pins of the active device.
The slewing scenario that I gave was simply based on the typical maximum slew rate spec of the LM3886 chipamp, 19 V/us (rounded to 20 V/us), for one of the 40V rails; not even particularly fast or powerful, as power amplifiers go.
And yes we do need that speed, done with highest accurately, so that as many of the Fourier components as possible end up with the correct amplitudes and phase angles, so that leading edges of transients are correctly and accurately rendered by the active devices.
Yes, and Ott or someone mentioned that orienting the MLCC layers perpendicular to the planes helps in some way, too, and is practical with certain ones that have more-square cross sections.
"It made absolutely no difference" when measured how and with what?
If it was your ears that's fine but then the most you can say is that the difference was not audible, to you, or not noticed by you, for certain source material, and with the rest of your equipment. That's certainly of some interest but please note that it's impossible to infer, from statements like that, that the current discussion even might be the slightest waste of time and effort.
Would you mind describing the physical dimensions of the capacitors in question and the types and dimensions of their interconnections and those of the devices they were meant to decouple? It's actually impossible to get any information that's relevant to the current discussion from your statement, without that data.
Also, you said that the amplifier "originally had 3 x 33000uF caps per rail". Did you change that?
I should probably say that MY primary end goal is the most-accurate reproduction of the source material, whether I can hear the difference or not, and even if it sounds worse to me.
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X2Ys are a subset of IDCs.
I didn't see anything about the inductance of paralleled caps in the PDF you linked to. I'll just take a handful of small electrolytics to work and look at them singly and in parallel with one of our Agilent network analyzers, and maybe also with my handheld LCR analyzer that can use excitation frequencies from 100 Hz to 10 kHz, since our network analyzers probably don't go that low.
Look at a DAC output with an oscope sometime. On a hard transient like a snare the FIR oversampling filter's sync response produces sizeable ringback; a realistic worst case is something around 70% of the DAC's swing between samples. At 44.1 that's about 125mV/us for a typical 2V DAC. Follow it with a typical 30dBish gain power amp and you get about 4V/us into a typical 4 ohmish speaker, or 1A/us. This implies a peak SPL in the 115 to 120dB range which is a bit unrealistic for home audio---90 to 100dB is more typical, implying more like 100mA/us---but people do crank it that hard. With point source speakers supply induced distortion in the amp's likely swamped by the driver distortion at 110+dB. But if one has a line array and a determination to destroy one's hearing...
Obviously, the numbers here vary for different scenarios and one needs to identify the corners of the design space of interest. I'm sure someone will decide they want to build a power supply for a 140dB KISS concert using ESLs.
What is the point of the above? Are you seriously trying to make the case that we shouldn't even try to create a high-fidelity audio power amplifier with a bandwidth of 160 kHz or even 320 kHz or so, just because some apparently-crappy digital audio technology can't take advantage of it, or because it might be "too loud"?
The slew rate scenario I was using, merely as an example, wasn't even for a high-end power amplifier. It was derived from the LM3886 chipamp's "typical" slew rate specification of 19 V/us (rounded to 20), assuming a 40V rail and a 4 Ohm speaker. (Of course that scenario is probably somewhat unrealistic for that chip, unless we cut the rail voltage in half, or double the load resistance.) But there are many discrete-transistor consumer-grade audio power amplifiers with maximum slew rate specs that are well over 100 V/us, with much higher voltage rails. I am not here to question their reasons for existing.
I do not believe that a 0.1 uF decoupling capacitor will hold sufficient charge to drive 4 Ohms from 0 Volts to 20 Volts in one microsecond, while disturbing the power rail's voltage by 0.1 Volt or less.
It seems clear that if we didn't have to worry about inductance, then the capacitance needed for that would be at least di dt / dv = (5 Amps)(1 us)/(0.1 V) = 50 uF.
We can also say that the target impedance of the decoupling network should be dv / di = 0.1 V / 5 Amps = 0.02 Ohms, at least up through the frequency implied by the risetime, f = 1 / (Pi x trise) = 318 kHz.
And we also know that the impedance of the decoupling capacitor and interconnects is something like Z = sqrt(L/C) + ESR + trace resistance, where L includes the inductances of the traces and leads (and ESL, if it is different than the L of the capacitor's leads). Since we know C and the target Z, we should be able to solve for the rest to see if it's even likely that we can make the connections short-enough to have low-enough parasitic inductance and resistance to enable us to hit the target impedance:
If we lump the ESR and trace resistance into "R", then
L = C ((Z - R)^2)
L = ((0.02 - R)^2) x .000050
The dissipation factor (DF) for a small 50V electrolytic is around 0.1.
ESR = DF/(2 Pi f C), within 100% or so over frequency
So at 318 kHz the ESR of a 50 uF 50V cap would be about .001 Ohm. So now
L = ((0.019 - Rconductors)^2) x .00005
I'd love to go back and turn that into an equation solved for the maximum round-trip length of the leads and traces, with constants in place for everything else, but don't want to get bogged down at the moment.
If Rconductors = .001 Ohm then L = 16 nH (or less).
Ruh Roh! If that's roughly 1 inch of conductor, round trip, WITHOUT taking into account the cap's ESL (maybe 2 to 10 nH), the layout might be "difficult", especially with through-hole caps.
I'm thinking that the solution, at least in more-difficult cases, would be to use parallel caps with non-coincident (non-shared) connections to the pins across which the decoupling is needed. That way, the TOTALS of the ESR and ESL and trace inductances and trace resistances should all be reduced in the same way that the total resistance of parallel resistors is reduced, compared to the individual resistances.
I'm with you on that and don't believe that "personal preference" should ever trump trying to provide the most-accurate reproduction (of which, however, that doesn't seem to be a good example).
Well Done, G.
you are showing without complicated maths that a bit of thinking can illuminate what happens at different frequencies around the Power Pins of amplifiers.
It is clear from your expose (how does one add a ' above an e to make it sound A) that distance has a very big role in effectiveness of decoupling.
I have tried, successfully, adding 0.1" pitch 100nF ceramics directly across the power PINs to a floating decoupling ground with a very tight area and very short lead lengths.
I could not hear any "ceramic" sound. I could not hear any tendency to ringing.
I could see a small difference on the scope, cf to no HF decoupling.
you are showing without complicated maths that a bit of thinking can illuminate what happens at different frequencies around the Power Pins of amplifiers.
It is clear from your expose (how does one add a ' above an e to make it sound A) that distance has a very big role in effectiveness of decoupling.
I have tried, successfully, adding 0.1" pitch 100nF ceramics directly across the power PINs to a floating decoupling ground with a very tight area and very short lead lengths.
I could not hear any "ceramic" sound. I could not hear any tendency to ringing.
I could see a small difference on the scope, cf to no HF decoupling.
Thanks all for the helpful and refreshingly friendly thread,
Couple of comments:
I have found that power / ground planes reasonably implemented are good to at least 100Mhz (my measurement limit). So if one has the luxury of such planes then lower frequency by-pass capacitors in my opinion do not need to be physically close to the part being decoupled. If you can extend the power / ground plane out to lowly populated areas of the board you can simply add low Q ceramics at will. You do need to insure sufficient power / ground plane capacitance to maintain the low impedance over the entire frequency band.
Gootee, I'm not yet convinced about your slew rate numbers as a starting point for the bulk capacitance. I understand the need for a fast amp but I dont see its speed as being the same as the large signal to the speaker.
It seems to me that not only are there physical barriers such as the cable inductance but that the music signal itself does not start with these rates, but rather more on the order of <1V/us (just a generic high value, of course there are power and efficiency requirements needed). I see the high amplifier slew rates as internal to the Amp and used to "keep" the output as close to the input as possible, such that these faster rates are small distortion correction signals. Such a wide power bandwidth will require a fast slew rate but I still dont see how that would result in full signal level slew rates currents seen by the supplies.
Thanks
-Antonio
Couple of comments:
I have found that power / ground planes reasonably implemented are good to at least 100Mhz (my measurement limit). So if one has the luxury of such planes then lower frequency by-pass capacitors in my opinion do not need to be physically close to the part being decoupled. If you can extend the power / ground plane out to lowly populated areas of the board you can simply add low Q ceramics at will. You do need to insure sufficient power / ground plane capacitance to maintain the low impedance over the entire frequency band.
Gootee, I'm not yet convinced about your slew rate numbers as a starting point for the bulk capacitance. I understand the need for a fast amp but I dont see its speed as being the same as the large signal to the speaker.
It seems to me that not only are there physical barriers such as the cable inductance but that the music signal itself does not start with these rates, but rather more on the order of <1V/us (just a generic high value, of course there are power and efficiency requirements needed). I see the high amplifier slew rates as internal to the Amp and used to "keep" the output as close to the input as possible, such that these faster rates are small distortion correction signals. Such a wide power bandwidth will require a fast slew rate but I still dont see how that would result in full signal level slew rates currents seen by the supplies.
Thanks
-Antonio
I had the impression you were wondering if 10A/us was a reasonable figure of merit. Guess I was wrong. I'm also not understanding how a practical upper bound on current slew got turned into a suggestion of 100nF as a total bypass size but, just to be clear, it's not. I anticipate extending the transient based model you're currently working with to account for ripple and PSRR will suggest sizes larger than O(100uF); we'll see what you come up with.
Anti-parallelling caps in separate packages creates a certain loop area due to the spacing between the parts. Interdigital capacitors shrink the loop by compressing the structure into one package. To put it another way, they're an implementation of the structure you've just arrived at, though usually one pours planes rather than using traces due to the inductance you've also just noted.
To be clear, so far as audio amps go I personally find it more effective to regulate the control loop than try to wring out incremental improvements from counting pH on the supply. The portion of this thread about bypassing for amp transients uses many of the same concepts as the portion where marcee and I are enjoying discussion of bypassing supplies in the low GHz range. But a four order of magnitude difference in operating frequency does have a way of shifting design priorities.
Thanks. It's just something that I've been wanting to understand better, for a while now. In some cases it will be "tilting at windmills" but if the requirements are properly defined it should be a useful method to know.
I've been wanting to try to DIY two power planes and a ground plane. How thin does the FR4 have to be? Would it have to be 20 mils or would thicker still be beneficial enough?
I could do it "the right way" and use a board house for fabrication but I'd like to also try it the cheap way, hand made, so others could easily do it at home, too. The layout might be painful, since I'd have to drill large-ish holes to allow hand soldering on layers below the top one, and would have to etch out areas for leads to pass through, and would have to hand-solder wires in place to make vias. But the benefits might make it worth doing.
I was thinking of one two-sided board sandwiched between two one-sided boards, glued together after all of the drilling and etching.
Hi, Antonio.
Actually, I was talking about the decoupling capacitance at the point of load, not about the bulk (main smoothing) capacitance.
A sinusoid of 22 kHz has a maximum slew rate of about
0.138 x (amplitude, 0-to-peak) (in Volts per microsecond)
since
slew rate max of sine = [(2 x Pi) x (freq in Hz) x (volts amplitude)] / 1,000,000
I have an amplifier that does up to 400 Watts average per channel into 4 Ohms, from 10 Hz to 20 kHz. That implies that Vavg^2/4 = 400, or Vavg = 40, which implies that Vpeak = 56.57 Volts, which would make the maximum slew rate of a 20 kHz sine output be 0.126 x 56.57 = 7.11 V/us.
So your 1 V/us is a little too low. That would imply a peak voltage of only 7.25 Volts at 22 kHz, and an average sinusoidal voltage of only 7.25 / sqrt(2) = 5.12 Volts, which could then only push 6.56 Watts average power into 4 Ohms, or 3.28 Watts avg power into 8 Ohms, at 22 kHz.
The other thing that people tend to forget about is harmonics. In light of Fourier's work, edges of transients will not be rendered accurately unless the higher-frequencies are available. Those frequencies might be well-above 22 kHz. Can we hear the difference if those frequencies are missing, or cannot be used accurately? I don't know.
At any rate, if the datasheet for something like an LM3886 chipamp says that it can typically slew its output at a maximum of 19 V/us, then why should we think that the decoupling capacitors should not be able to supply the transient currents needed to support that? It might not be needed for the music output, directly, but as you mentioned it might be needed for purposes inside the feedback loop of the amp. (I guess I'd have to chew on that for a while, to be able to decide if it makes sense or not. Maybe it could, in light of the presented load impedance or something.)
As far as the speaker cable load is concerned, they usually have quite low inductance, at the expense of having higher capacitance. So they should not limit the slew rate of the output, by very much, nor make it unnecessary.
You are totally correct that the resulting fast current slew rates should not have to be seen by the supply (which is a good thing, especially if the rails have any length to them, since their inductance would probably then cause a very large ripple voltage). THAT'S EXACTLY why the decoupling caps at the point of load need to be able to do it! That's basically been my main point, here, all along. i.e. I have been trying to figure out how to select the decoupling caps and how to position them so that even the inductance of their own local connection to the load (and with all of the other parasitics) doesn't make it impossible for them to deliver the worst-case transient current waveform with precise accuracy of timing and amplitude.
Cheers,
Tom
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Sorry. You and one other person mentioned 100 nF and I must have misunderstood the context.
The ripple has been mostly taken into account, already. In theory, we can make the ripple as small as we want, by using larger values of decoupling capacitance. I haven't touched on PSRR yet. (Not sure I know where to start, with that. Please feel free.
Ah. OK. See my other post where I mention wanting to try DIYing four layers for audio. Any thoughts on how to take best advantage of planes, for audio, if I do try it?
I don't understand. Which "control loop"? I'm guessing that you mean power supply regulation, and would then assume that you are implying something about controlling the output impedance of the supply, maybe so we wouldn't have to worry about what's upstream. Is that close? The simulations that I have been doing, mainly for decoupling caps and parasitics, have so far been done with a model of just the smoothing caps (and their interconnects) of an unregulated supply, with a fixed DC voltage upstream from them. Even then, there are huge effects from changing the properties of the smoothing cap network. So I should probably at least put in a typical DIYer's three-terminal regulator.
Yes, I could definitely enjoy it if you and marce did another couple of hours' worth!
Yeah. But when I first started thinking about audio circuits and systems, I assumed that it would all be relatively trivial, because the frequencies are so low. I was wrong. And seeking the difference between "good hi-fi" and "exquisite hi-fi", and how to implement the latter, can be very challenging.
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This intrigued me, because I don't see how, with the secondary path length significantly increased and the low magnetic coupling between two free standing conductors there could be an improvement.
Thus, I just gave it a quick actual test, based on typical configurations and form factors.
The results seem to confort my gut feeling: with the plain standard paralleling, there is a small improvement in the series inductance (-~20%), but the the effect practically disappears with antiparalleling.
This is a quick, informal test, and unlike the previous ones, still unpublishable at this stage.
I think however that it shows the general tendency: there might be geometric conditions where an improvement could be gained, but it would be very marginal, and obtained under very marginal conditions.
More on this later, when I'll make more systematic, standardized and reproducible tests on the subject.
Did he mean that one is decoupling the positive rail and one is decoupling the negative rail? Not sure how that would work but if the currents were flowing in opposite directions at equal magnitudes then maybe it would have some effect. It might also only or mostly apply to MLCCs, with the layers aligned correctly.
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