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Old 10th February 2012, 03:29 AM   #371
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Quote:
Originally Posted by marce View Post
High Density Interconnect, is the way forwad for PCB design and high speed layout. The board is also the capacitor.
http://www.laocsmta.org/archive/Embe...esentation.pdf
Scary close layer spacing, high dielectric, I'm all in favor but isn't it possible audio performance may actually take a hit in long term reliability and piezo electric effects?

Thanks
-Antonio
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Old 10th February 2012, 09:18 AM   #372
marce is offline marce  United Kingdom
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These sort of boards are for high speed digital. Personal preference and a scheme we follow where possible at work, is a digital board and an analogue board, with isolation. This is getting harder to achieve as things shrink down, and as always cost.
High dialectric layers cause there own problems, as speed of proagation goes down with increased dialectric constant. This reduces the effective area of the capacitive layers! This is only a concern at realy high speeds, but with DDR3 memory becoming standard and high speed FPGA's its standard these days. A friend of mine is doing a board where some signals can only be routed a max distance of 1". We often work on an area 20mm x 10mm zoomed to fill a 23" wide screen monitor.
I will have a look around and see if any research has been done on noise induced by piezo effects in HDI construction PCB's.
The chips embeded within PCB's are not wire bonded, but bump bonded, like tiny BGA's.
Tha advantage of having digital and analogue boars is so the construction of each can be optimised. Digital, high speed 10-16 layers HDI, thin copper (1/2oz and less), fine line design (0.004"/0.004" track and gap). Analoge (and power) less layers 4-8, heavier copper (2oz), heavier traces (0.010-0.100).

Last edited by marce; 10th February 2012 at 09:22 AM.
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Old 10th February 2012, 12:39 PM   #373
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Marce

Understand.
I was thinking along the lines of employing all th latest techniques to provide the best decoupling or by-pass (theorectically anyway as I could never justify or afford the price of the boads discussed), but you remind me that the best over the audio range (including all frequency just beyond the crossover) may not be the same as those intended to extend into the giga hz range.
Thanks
-Antonio
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Old 12th February 2012, 12:01 AM   #374
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Default Design of VDD bypassing for PowerAmplifier

Suppose we have a number of 10,000 uF caps, about an inch apart,
wired together with twisted_pair for minimum area and thus minimum
inductance.

Assume 10nanoHenry for the wiring between caps, the L*C product
is 10^-8 Henry * 0.01Farad or 10^-10. We square_root that and invert,
finding the radians/sec is 100,000 and the resonant freq is 16,000Hertz.
Definitely able to cause coloration. Note that bigger caps will also use
bigger wiring loops, and the resonant freq drops more and more.

So lets work with the 10,000UF and 10nanoHenry.
How to dampen that?
"wikipedia damping ratio" is helpful, with plots.
And "zeta" = 1/(2*Q)
At zeta of 0.7, we have no overshoot, {figure below bouncing spring}
after a surge of charge is pulled from the reservior capacitors.
The Q would be 1/2*zeta = 1/2*0.7 = 1.4, telling us the ratio
of inductive_impedance/dampening_resistor {also Xc/R}.
Let's just aim for Q=1, meaning Zl = Zc = Resistor. Simple. I like simple.

Xl=Xc at the ringing freqency; Xl = radians/sec * L = 100,000 * 10^-8
Xl = 10^5 * 10^-8 = 10^-3 = 1 milliOhm.
And an inch of #20 wire provides 1 milliOhm.

Thus, putting aside any use of ESR and solder_resistance and
skin_effect etc etc, we can use the wires to provide the dampening.

SUMMARY: aim for Q=1 (easy to remember), and aim for
1 inch or more of small wires between the caps to be resistive/lossy,
and thus reduce the coloration. In other words, huge wires are not
good for coloration. Surprise?

tank


#20 AWG solid wire is 10 ohms/thousand feet,
10 milliOhm/foot, 1milliOhm/1_inch.

Can we bring the 10,000 uF caps right up to the output transistors?
10nH is approx 20mm of wire; twisting VDD/GND together
will reduce the 10nH of VDD and 10nH of GND back to 10nH total,
and we now have 2 milliOhm of dampening.

We know the mechanical engineers design different brands of
capacitors differently, hence the internal inductance will vary.

Experiment with other caps right at the output transistor
collector_GND nodes,

L=10nH C=10,000uF Fring=16KHz Rdamp=1mOhm
L=10nH C=100uF Fring=160KHz Rdamp=10mOhm
L=10nH C=1uF Fring=1,600KHz Rdamp=100milliOhm

At L=100nH, freqs drop by 1/sqrt(10), and Rdamp increases by sqrt(10)

At L=1,000uH, freqs drop by 1/10, and Rdamp increases by 10X.

Thus with longer wiring, the dampening Rs should be larger in value.

How much power will discrete resistors dissipate?

Power = I*I*R, thus at 5amps RMS and 1milliOhm, the wire
dissipates 25 milliWatts---in the wire.

Unless we have an unstable amplifier, there will be little
energy at 160KHz or at 1,600KHz, and similar small dissipation
will occur in any discrete SMT dampening resistors.
I think. I have not done the math on this. Who wants to?

tank (All mistakes are mine)
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Old 12th February 2012, 06:17 PM   #375
gootee is offline gootee  United States
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Tank,

Cool! I can hardly wait to go over your last post and maybe also see how it ties in with the decoupling cap stuff I did earlier. Right now I'm still trying to beat a deadline for completion of some mandatory training for work. Bummer. But I hope to be able to get back to this as soon as that's finished, maybe by tomorrow.

Cheers,

Tom
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Old 5th March 2012, 09:11 AM   #376
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re: Cb = 50/pi*fc equation for op amp primary power supply bypass cap

Graeme contends that the 1-ohm guideline almost always assures stability, therefore
ZCb = 1/2*pi*f*Cb = 1 ohm
gives
Cb = 1/2*pi*f
Selecting f = fc/100 gives the general equation Cb = 50/pi*fc
My understanding is he advocates f << fc to make analysis easier, as it negates much of the parasitics.
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Old 8th March 2012, 11:00 PM   #377
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Excellent thread!

I soldered on a matrix board a line level active crossover with 6 x OPA627 opamps tightly lined up together supplied by LM317/337 regulators with 16AWG wires for both rails and ground in a short distance (less than 100mm). I had 3 x 2,200uF after the LM317/337, and 4 x 100uF electrolytic caps and 4 x 0.1uF MKP caps soldered directly on the 16AWG wires close to the opamp supply pins.

I EXPECTED resonances on the rails at some higher frequencies.

However, my old oscillioscope with limited resolution (I can see 1mV ripples up to 10MHz) did not show any resonances from 20Hz to 10MHz. All I saw was only a flat line.

I then connected a CD player to the active crossover and played some music. It appeared that this did not trigger any resonances on the rails, as what I saw on the oscillioscope was still a flat line.

Does this mean that parallelling capacitors in this particular case happened to work well for me? or my measurement equipment is not good enough?

Regards,
Bill
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Old 9th March 2012, 01:39 AM   #378
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10MHz is pretty low, but then so is 20kHz. It's also likely the OPA627s are operating class A; you might want to check on that.
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Old 9th March 2012, 04:37 AM   #379
gootee is offline gootee  United States
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Yes, 10 MHz is too low to declare that there is not a problem. Sometimes that's around the point where the impedance seen by the power supply pins is just starting to increase rapidly. Someone on another thread somewhere mentioned, a day or two ago, that they had a strong oscillation at 300 MHz.
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Old 9th March 2012, 09:57 AM   #380
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opa627 has a GBW of 16Mhz. For resonances beyond that point I am not sure if they affect the opamps. I guess if there are any resonances up to 16Mhz, I would not see a flat line, would I?
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