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Old 4th January 2012, 11:32 AM   #331
marce is offline marce  United Kingdom
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Hi Tom et all, a happy new year.
I will try and catch up with this thread over the next few days, as I have had some time away from it all to sort a few things out, and seem to have missed a lot.
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Old 6th January 2012, 04:40 AM   #332
gootee is offline gootee  United States
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Thanks! Welcome back, Marc, and Happy New Year!

I've had to work some evenings and weekends to take care of some things for work and haven't had time to finish the simulation stidies I was playing with. It looks like I won't have any time for it until at least after this weekend.
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Old 15th January 2012, 02:09 AM   #333
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I too worried about parallel resonances of power capacitors.

As newbie, I was given a design to cleanup hahah. Actually the senior guys
wanted me to learn about parallel-cap resonances. Twas a pulse
amplifier, for Sandia, to be "flat" from 100KHz to 100MHz (I think).
Using some HP spectrumAnalyzer+TrackingGenerator, a dip appeared
at 47MHz. I had not a clue.
The senior guys gently suggested I examine the 100UF and the 0.001UF
on the +15volt line. LO and BEHOLD, 10nH inductance (of the 100UF)
and 1,000 pF do indeed resonate near 47MHz. I got enlightened a bit.

Am still getting enlightened, decades later.

Since the larger capacitor does not set the resonant frequency, we may
instead view it as a source of losses. And ESR of 1 ohm at 47MHz has what
dampening? Impedance of 1,000pF at 50MHz == 0.128 ohm. Thus even
0.1 ohm resistive losses would have killed that 6dB notch in the frequency
response. That 100UF sealed tantalum electrolytic was rather low loss!

Hmmm a way to measure HF losses? use an RF sweep generator, with 50 OHM
Rout, into two paralleled caps, and measure (with scope?) the signal across
the smaller cap? or across the bigger cap?
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Old 15th January 2012, 02:56 AM   #334
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Consider adding a SNUBBER (dampener).
The goal: ensure some lossy behavior at all frequencies,
regardless of capacitor internal losses (or lack of losses).
Thus compute what dampening R you want (0.1 ohm ?)
and include that in series with 1,000UF and with another 10UF
and with a third 0.1UF cap.

Ah. Alternative. Cute. I'd forgotten. PCB resistance may be adequate.
At 1/2,000 ohm per square, a 10mil by 500 mil trace has 50 squares
and thus 50/2,000 = 1/40 = 0.025 ohm. {this for standard 1-ounce foil}

tank
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Old 15th January 2012, 04:38 AM   #335
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"Any capacitor would (within reason) do the job if it was just capacitance that was to be considered, but the series ESL is the problem. That is why small physical lower value packages are placed next to the device pins, as the parasitic inductance is low they can supply the almost instantaneous requirement for current, then moving further away from the device power pins the larger reservoir caps, supply the next current requirements, then the power supply output cap(s), then finaly the voltage regulator, this being the slowest to react."

A perspective on inductance. 1nanoHenry at 1GegaHertz (I used to
do RFIC design) is j6.3 ohms. That is a problem for many designs.

1nH at 1MHz is 0.0063ohm
10nH at 0.1MHz is 0.0063ohm
10nH at 0.02MHz is 0.0012ohm.

Pulling 5 amps at 20KHz thru 0.0012ohm
is only 0.006 volts drop.

Thus with a 60 volt rail, we have -100dB effect (10^-5).

I expect the resonances {this thread is very valuable for that}
are more the problem, than the remaining small Ls.

tank
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Old 15th January 2012, 05:43 AM   #336
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[QUOTE=gootee;2835337]Couldn't we make the power supply impedance appear to be arbitrarily low, to the load, with this technique, i.e. just by adding more parallel power and ground rail conductors, each with another decoupling capacitance? (within the limits of the available PCB real-estate, at least) I believe that we could.


The challenge then becomes connecting to a PowerTransistor
with a single Collector pin, and single Emitter pin (our high dI/dT pins).

Perhaps design PCBs that provide GNDplane (Vdd plane?)
up to the Collector, with 0.1uF 100volt ceramic X7Z lossy cap
from Collector to GND, with short vias.

Since the heat gotta be removed, probably bend the leads at
90-degrees, and bring stripline Power/GNDplane PCB along
at 90degrees to HeatSink. Maybe have 3rd layer that's Vout.
Or even 4th layer, of -Vdd.

tank
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Old 15th January 2012, 10:21 AM   #337
AndrewT is offline AndrewT  Scotland
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What you are describing is the collector to collector (of an EF pair) that are connected together via pair of series connected low value low inductance decoupling caps. The cap junction is effectively power ground for the VHF pulses.
That route: collector to cap to VHF Power Ground to cap to collector must be very short to minimise inductance.
This is the battery that Gootee uses as an analogy.
Assume that no speaker current comes from the PSU nor does any VHF current come from the on board electrolytics. All the VHF current comes from those two decoupling caps. Think of them as VHF batteries. Design the layout and the routing to maximise the VHF current available to flow around that tiny figure of 8 PSU.

As an aside, I believe the output Zobel that is required to help with HF stability must also couple into that VHF current route. I think that locating the Zobel further away than necessary, reduces the effectiveness of the stability enhancing duty of the Zobel.
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regards Andrew T.

Last edited by AndrewT; 15th January 2012 at 10:24 AM.
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Old 15th January 2012, 11:42 AM   #338
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Dear Gootee wrote:


Quote:
Something that occurred to me, earlier today, about the 100/120Hz ripple voltage in a linear power supply: It seems like maybe we could just disconnect (or shunt-away) the rectifier output, whenever the capacitors are "full", i.e. when the voltage is already at the desired level. And then when the voltage dips, slightly, due to the load drawing some current, we could allow the rectifier to provide JUST enough current to recharge the reservoir caps. That way, NO 100/120Hz ripple voltage should EVER get past the reservoir caps. And knowing the sizes of the caps in advance and sensing the voltage differential to be corrected, as it occurs, we should be able to precisely meter-in the correct number of electrons, with the correct speed profile, exactly when needed. Of course, a good implementation would start to crack open the current valve whenever the voltage just started to dip, and voila, perfect constant DC voltage should result (AT the caps, at least). Maybe that means using a smart preregulator of some sort. We could probably also sense the voltage farther downstream (at the load), with a pair of conductors that didn't carry much current (so their sensing wouldn't be affected much by their parasitic inductances and resistances), and anticipate the effects of the inductances and resistances of the main current-carrying rails, and adjust the cap-recharge valve's dynamic response accordingly. It seems like a fairly-straightforward control-system problem, if a decent basic hardware control mechanism could be implemented. [Are there any 3rd or 4th year BSEE students lurking, who are taking (or have just taken) classical feedback control theory? A closed-form mathematical expression of the problem and solution would be nice.] Then again, who cares about anything but what happens at the point of load (and also, nothing interesting is happening when the caps are staying full, anyway)? So maybe the preceding idea should be applied at the decoupling caps or the point of load, instead of worrying about the ripple at the main caps. Or, we could do both. <smile>
If I understood well, this circuit, created by -ECdesigns- for low power uses but adapted by myself also for higher power, goes on that direction on a different aproach and could also be able to get rid of the HF noise from the rectifiers...

https://picasaweb.google.com/lh/phot...eat=directlink

It works very well on my Class AB and UCD power amps...

https://picasaweb.google.com/lh/phot...eat=directlink

Cheers,
M.
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Old 15th January 2012, 03:54 PM   #339
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We can exploit the skin-depth of PCBs, to ensure high dampening
at high frequencies. Somewhere around 5MHz, standard-thickness
foil begins to increase in resistance because the "self-inductance"
(view the foil as having myriad internal threads of current, all
generating Hfields) begins to crowd the current toward the surface.

And surface-roughness only increases the resistance.

At 50MHz, foil is 1.5milliOhm per square.

At 500MHz, foil is 5 milliOhm per square.

Then we can wonder about the HF losses (our friend) of
the solder-plated capacitor leads.
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Old 16th January 2012, 02:06 AM   #340
gootee is offline gootee  United States
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[QUOTE=tankcircuitnoise;2862592]
Quote:
Originally Posted by gootee View Post
Couldn't we make the power supply impedance appear to be arbitrarily low, to the load, with this technique, i.e. just by adding more parallel power and ground rail conductors, each with another decoupling capacitance? (within the limits of the available PCB real-estate, at least) I believe that we could.


The challenge then becomes connecting to a PowerTransistor
with a single Collector pin, and single Emitter pin (our high dI/dT pins).

Perhaps design PCBs that provide GNDplane (Vdd plane?)
up to the Collector, with 0.1uF 100volt ceramic X7Z lossy cap
from Collector to GND, with short vias.

Since the heat gotta be removed, probably bend the leads at
90-degrees, and bring stripline Power/GNDplane PCB along
at 90degrees to HeatSink. Maybe have 3rd layer that's Vout.
Or even 4th layer, of -Vdd.

tank
Thanks. Interesting.

Yeah, with multiple-layer boards, you can do things "the right way". My comment was aiming more at methods that could potentially be used to get some (or at least one) of the same benefits when doing DIY construction at home, with one-sided or two-sided PCBs.
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