paralleling film caps with electrolytic caps

[twest820]

Originally Posted by gootee

What is the significance of phase angle or group delay, in a plot of the impedance seen by the amplifier power/gnd pins?

If the amplifier in question's a switchmode regulator or LDO it can be the difference between stability and instability, though usually one's just tuning the parts selection to maintain good phase margin (transient response) across the design corners. In the case of a signal amplifier you get (supply stuff)/PSRR on the output as discussed quite a bit over the last couple pages of this thread.

For analog audio I don't see a case in which supply phase considerations are signficant; reservoir caps turn inductive around 100kHz, sufficiently far above the audio band as to be irrelevant (assuming sufficient high frequency bypassing to keep the signal amp stable and off its slew rate). The same tends to hold for DACs. If you apply the -80dBish target I discussed a few posts back that means about a 10ns RMS jitter budget in 16/44.1. Low cost DACs come in around -100dB THD and, as I mentioned a few posts ago, it's not hard to build a supply which supports -110dB. That means that, among other things, if you don't want playback system performance to limit on the DAC you have a jitter budget in the range of 300ps to 1ns, halving for every clock doubling and extra bit. An ES9012 or ES9018 at 192kHz wants less than 20ps RMS to hit its -120dB THD and 3ps for its -135dB DNR in mono. Phase jitter from a decent XO with standard MLCC bypassing is around 3ps over 10kHz-20MHz, increasing a couple hundred fs if the integral's taken down to 10Hz. So, from the standpoint of an asynchronous DAC with a dedicated XO, the supply's essentially a non-problem and one's better off paying attention to impedance control and termination on the clock line to minizmise ISI.

More complex clock topologies create more complicated requirements. The limiting factor in generation is more often the supply than the clock itself. See, for example, table 1 in this thesis (page 26) as well as the design collateral for National/TI's LMK and LMX parts and TI's higher end CDCE parts. The femtosecond clock generators all use on die bypassing, on die regulation, and split external supplies and bypassing to improve performance. While overkill for audio there's a two or three order of magnitude performance gap between these and the low cost clock generators which come in at 100+ps (TI CDCE90x, for example). The low cost generators use similar split supply topologies but seem to lack the on die regulation of the higher cost parts. This implies one could perhaps get better performance out of the parts by devoting more cost to the external supplies. For example, the CDCE906 datasheet shows a phase noise hump between 2kHz and 500kHz which I suspect could be mitigated with a good local regulator with a large output bypass---perhaps a LM1117 followed by a Nichicon L8, S8, or R7. This is perhaps a bit quirky, but the 114dB DNR CS4365 is $6.24 in DIY quantities and the 120dB DNR ES9006 is $9.50. So spending more on the supply of a low cost clock gen to get more out of these parts could produce an interesting design win. If you could get the jitter down to 10ps-ish then hitting the ES9006's DNR should be doable at 192.

Originally Posted by gootee

Here's one that claims to prove that multiple decoupling/bypass values are better than multiple caps of the same value.

Yup. The model seems a bit idealized in that it's assumed all 100 caps are identical and have identical plane/trace impedance---they won't due to placement geometry and process variation, though typical pick and place will pull 100 sequential caps off the reel and hence the tolerance will tend to be tighter than the speced +-10% or 20%. Also, what matters is what the die sees. That will include a certain ESR and ESL due to metalization, package pins, bondwires, DAP vias, and so on in addition to any on die capacitance. A typical bondwire's around 1nH and 200mOhm and metalization can be around a hundred mOhm as well. So adding ESR to the supply may not be needed. Particularly for the low pin count, bonded packages DIYers tend to favor.

[gorgon53]

Originally Posted by gootee

Here's one that claims to prove that multiple decoupling/bypass values are better than multiple caps of the same value (and that fewer caps can be used if they have higher ESR):

http://www.n4iqt.com/BillRiley/multi...ypass-caps.pdf

Cant see how this model could be of much use in a practical situation
where we will have substantial serial L and some R between the caps. Or did I miss something?

[twest820]

Originally Posted by twest820

The same tends to hold for DACs.

Argh, the above analysis is incorrect as I forgot to allow for noise shaping via over or upsampling. That pushes one or two orders of magnitude of jitter out of band, so the above numbers are 20 to 55dB high. Should mean even fairly low quality clocks (~100ps jitter) aren't a problem. #nevermind

[gootee]

Originally Posted by gorgon53

Cant see how this model could be of much use in a practical situation
where we will have substantial serial L and some R between the caps. Or did I miss something?

I guess it depends how they're connected. Also, he did mention including at least L for traces, at one point. But I haven't looked at it in detail.

If the caps were spread over a ground plane and power plane, their currents might all take different paths. So then the Ls and Rs would only be in series with each cap, not between them.

[gorgon53]

Originally Posted by gootee

I guess it depends how they're connected. Also, he did mention including at least L for traces, at one point. But I haven't looked at it in detail.

If the caps were spread over a ground plane and power plane, their currents might all take different paths. So then the Ls and Rs would only be in series with each cap, not between them.

They will take different path, lol. Maybe be we can ignore R in a ground/power plane situation but can we really totally ignore the inductance as well?
After all, caps leads arent ideally positioned and the inductive loops connecting the caps are of considerable mechanical dimensions. Offcourse, if the ground/powerplane could be arranged at a distances comparable to those inside the caps things would be different. But I cant see how this could be done.

[gorgon53]

Btw, by contolling the currentflow by cutting out "stripes" in the power-plane can result in lower serial L between the caps at the cost of increasing R and this will lower the Q

[gorgon53]

controlling, not contolling, sorry, am gettn blind at this time of the day

[gootee]

Originally Posted by gorgon53

They will take different path, lol. Maybe be we can ignore R in a ground/power plane situation but can we really totally ignore the inductance as well?
After all, caps leads arent ideally positioned and the inductive loops connecting the caps are of considerable mechanical dimensions. Offcourse, if the ground/powerplane could be arranged at a distances comparable to those inside the caps things would be different. But I cant see how this could be done.

Seriously, the currents from the caps to the decoupling points can all (or mostly) take slightly-different paths, if the caps are spread out well-enough, on the planes. There are several recent papers (e.g. Archambeault) showing this effect, where many caps are placed in several types of placement patterns, which are compared, so that the effect becomes more obvious. I am guessing that it is like Ott pointed out in the latest version of his EMC book, i.e. the inductances of parallel caps will reduce like the resistances of parallel resistors do, but will "fully" do that only if there is no MUTUAL inductance, and am guessing that was one of the assumptions made in this paper, i.e. separate current paths for all decoupling capacitors.

And as I mentioned, he (Douglas Brooks/Ultracad) did not ignore the parasitic inductances, nor the resistances. I haven't read the paper in great detail, but I did see where he mentioned that the L and R of the traces or planes was included. (I believe that he may have lumped the trace parasitics with the C parasitics, which would be valid, algebraically at least, if the capacitor currents all took separate paths, although the magnitudes of the parasitics would obviously need to be different than those of just each C alone.)

I am not sure if he is correct or not. But I don't think the results can simply be completely discounted, quite so easily. However, as in every other study of multiple decoupling caps that I have seen, at least the ones where any possibly-useful conclusions can be drawn, certain assumptions are either made or are implicit in the setup. Archambeault's stuff looks fairly good, in that regard, and probably better than this one, or at least better-explained. But at the moment I can't quite remember if I have seen where he ever examined this same type of question.

And the parts about higher-ESR caps making wider minimi and maximi, which are also less extreme, seems valid and potentially useful (although I guess we all already knew about that).

[gorgon53]

gootee, I am with you that the results should not be discounted, and a useful model would be very valuable. My "lol" was nearly because I found it funny that anyone would even presume that the currentpaths, currents a.s.o would be evenly distributed without
a carefully thougth through layout. What I could not find in the model is that provision is given to the layout dependend L and R in the planes. It will also have to include the current- and frequency dependenc (skin,proximitie,flowdirection,Dk, lossfactor a.s.o). I find the influence of R on damping and the results from paralelling L to be very basic stuff and offcourse they are valid and usefull, I fully agree.

[gootee]

I was thinking about the application of the parallel capacitance idea to the smoothing capacitors in an unregulated linear power supply. And I wondered how much benefit there might be to keeping the traces separate, all the way to the point of load, to that their inductances (and ESRs) would tend to reduce by being in parallel (the way that the total resistance reduces when resistors are in parallel).

I simulated the two circuits shown, and plotted the impedances as seen from the loads.

The "shared traces" version (second/bottom circuit) has about 50% higher impedance, at lower frequencies, and gets much worse at higher frequencies.

By 10 MHz, the "shared traces" version is up to almost 4 Ohms while the paralleled version is only up to about 1.4 Ohms.

The inductors are each simulating two inches of some conductor with 15 nH per inch and 0.001 Ohm per inch. Each capacitor has an ESR of 0.05 Ohm and an ESL of 5 nH.

ps_imped_ckt.JPGps_imped.JPG