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Old 5th December 2011, 01:08 AM   #221
gootee is offline gootee  United States
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Calculating values for decoupling capacitors:

The classic equation for capacitor behavior is

i = C dv/dt .

So we should be able to use

C = Ipeak (delta t / delta V)

where delta V is the desired or allowed maximum drop in voltage across the capacitor when we need Ipeak amps with a risetime of delta t seconds.

Another form of that equation is

C = (delta I) / (2 Pi f deltaV), where f is frequency.

We also know that the maximum derivative (aka slope, aka slew rate) for a sine wave is

slew rate max of sine (in volts per microsecond) = [(2 x Pi) x (freq in Hz) x (amplitude in volts)] / 1,000,000

So, for example, if one side of an amplifier can slew 20 V/us for 2 us, with a 4 Ohm load, that would be 10 amps in 2 us, and the minimum required decoupling capacitance should be

C = Ipeak (delta t / delta V) = 10 A x 2 us / delta V

If we choose delta V to be 0.1 Volt, then C = 200 uF.

The alternate equation involving f gives double that C value (for the corresponding f = 39.75 kHz) so it must be giving the total capacitance for both rails, assuming a rail-to-rail swing, or else I was off by a factor of two in my frequency calculation.

We also know that for an inductor,

V = L di/dt .

So we should be able to approximate that as

L = Vpeak (delta t / delta i)

which for the above case gives

L = 0.1V x (2 us / 10A) = 20 nH,

which should mean that there needs to be less than or equal to 20 nH of inductance, total, which would include at least the capacitor's internal inductance plus the inductance of the capacitor's leads, the pcb traces or wires, and the amplification device's power and ground leads, for the path that runs from the amp device through its power pin then through the cap and the amp's ground pin.

Using the rule of thumb that every inch of PCB trace has about 20 nH of inductance, and guessing about 5 nH for the capacitor's inductance, that would mean that the total round trip distance could only be 0.75 inch (about 18 mm), i.e. including the PCB traces and the amp device's power and ground leads!

For a better estimate of trace inductance, use Equation (2) at Analog Devices : Analog Dialogue : PCB Layout .

It also looks like an upper bound for the maximum ESR of the cap (ignoring voltage across the internal inductance of the cap, for the moment) could be

ESR < 0.1V/10A = 10 mOhms, at 39.75 kHz, for our example.

ESR changes significantly with frequency, but DF (dissipation factor) should stay within about a 2:1 ratio, typically.

DF (aka Tan(delta)) = 2.Pi.f.C.ESR

Here, still ignoring the voltage across the cap's internal inductance, an upper bound for DF for the 200 uF cap would be about

DF = 2 x Pi x 39750 x 200 x 0.01 = 0.50, for our example.

Since most electrolytics have ESR spec'd only at 120 Hz, we can calculate the ESR(120Hz) based on the DF and the ESR@39.75kHz, to get an upper bound for the ESR spec @ 120 Hz.

ESR = Df / ( 2.Pi.f.C) = 0.5/(2.Pi.120.200u) = 3.3 Ohms max @ 120 Hz, for our example.

Pulling a number out of the air for the capacitor's inductance, 5 nH, would give a voltage contribution across the cap of about

L x (delta i) / (delta t) = 5n.10A/2u = .025V, for our example,

leaving 0.075V to be induced across the ESR, if we want to maintain our chosen 0.1-Volt change across the capacitor.

That would give a max ESR estimate @ 39.75 kHz of 7.5 mOhms, giving a DF of 0.37, which would give an maximum ESR@120Hz spec of 2.45 Ohms. But since the DF could vary by a factor of 2 or so, it should be safer to look for a 200 uF capacitor with a maximum ESR of about 1.2 Ohms at 120 Hz.

Sorry if there are arithmetic or math (or other) errors. I was just making this up as I went.

I still need to simulate or test all of this stuff, to see if it's even close to being accurate.

Last edited by gootee; 5th December 2011 at 01:37 AM.
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Old 5th December 2011, 01:45 AM   #222
gootee is offline gootee  United States
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Yeah, I think I used peak-to-peak amplitude to calculate the "equivalent frequency" from the max slew rate, when I should have used 0-peak amplitude. I still can't remember which way is correct but I'm guessing 0-peak is the "amplitude" that I used when deriving the max slew rate equation. So a bunch of stuff in the example might be off by a factor of either 2 or 1/2.

Last edited by gootee; 5th December 2011 at 02:03 AM.
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Old 5th December 2011, 04:56 PM   #223
AndrewT is offline AndrewT  Scotland
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The matter of whether the example has an error of 2 or 0.5 can be sorted later.

What really matters, to me, is that the analysis shows that a 1us 10Apk signal can be supplied by a ~220uF cap, if esr and inductance are low enough.

By scaling we can see that a 10Apk 10ns pulse can be supplied by a 2uF cap. and similarly that a 10Apk 1ns pulse can be supplied by a 200nF cap wrapped very closely around the device terminals.
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Old 6th December 2011, 05:12 AM   #224
gootee is offline gootee  United States
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It's a beautiful thing, eh?!

(But I think it was a 2us, not 1us, 10aApk signal that could be supplied by a 200 uF cap.)

I received the Henry W. Ott book (Electromagnetic Compatibility Engineering, 2009 revised edition) in the mail, today, and when I first cracked open the 843-page book, it opened to the section on decoupling.

One immediate tidbit: Rise time and frequency are related by:

trise = 1 / (Pi f)

or

f = 1 / (Pi trise)

And, of course, the best decoupling will happen at the resonant frequency of the series capacitance and parasitic inductance, since the impedance will be at a minimum at that frequency, which is given by

f = 1 / ( 2 Pi sqrt( L C ))

For fun, I decided to combine those two equations, to try to get an equation for the "optimal" C value (impedance-wise, only) to use for a given rise time, given the total parasitic inductance. Substituting the expression for f from either equation into the other gives

C = ((trise^2) / 4) / L

For your 1 us trise example, that comes out to about C = .00025 / L , if L is in nH. It seems a little odd that we have to make L = 1.25 nH befoe it gives C = 200uF. But of course it blows up to infinity for L = 0. Unfortunately, for practical values of L, the C is relatively small. For example, with 30 nH, it would be about 8.33 uF.

----------------------

I haven't finished Ott's decoupling material, yet, but have read enough to see that using multiple identical decoupling caps is a good idea (and multiple different-valued caps can be bad). He's describing it in the context of digital circuit applications, but it looks more-broadly applicable.

Note that by paralleling n caps, the total capacitance is multiplied by n and the total inductance is divided by n, which are both in our favor. HOWEVER, the inductance will only divide by n if there is NO mutual inductance. That means that the "parallel" caps must not share the same conductors. They would either have to be connected by a "star" of sets of two conductors (all meeting across the power and ground pins to be decoupled), or be "spread out" and use power and ground planes.

We can take the allowable power supply rail transient voltage variation, dV, and the maximum transient current draw or current change, dI and calculate a target impedance,

Zt = dV/dI .

For our example of 10 Amps in 2 us with only 0.1 Volt of power rail disturbance amplitude, that would give Ztarget = 0.1V / 10A = 10 mOhms, which would need to be in place at least up to the f = 1 / (Pi trise) frequency of 159 kHz.

If we assume that each ideal capacitor has L = 30 nH in series with it, then according to Henry Ott we can calculate the minimum number of capacitors needed with

n = (2 L) / (Ztarget trise) (which, for our example, reduces to 0.1 x L, if L is in nH) = 3 capacitors .

Mr. Ott notes that one key to optimum decoupling design is knowing what inductance to use in the equation above.

Since the magnitude of the impedance of a capacitance is Z = 1 / (2 Pi f C), we can solve for C for a given Z (Ohms) and f as

C = 1 / (2 Pi f Z) .

Up to the frequency that is equivalent to the example rise time of 2 us, 159 kHz, we can calculate that in order to maintain our target impedance of 10 mOhms (0.010 Ohms), we would need a total capacitance of at least C >= 1 / (2 Pi 159k .01) = 100 uF

But below the resonant frequency, the capacitance must also be able to supply the transient current requirements,

C >= dI dt / dV ,

which for our example would be 10A 2us / 0.1V = 200 uF.

To satisfy both the impedance and transient current requirements, we would choose the larger capacitance of 200 uF and then divide by at least the minimum number of capacitors required, and would therefore need to use at least n = 3 capacitors of at least C/3 = 66.67 uF each.

So the answer (for an LM3886 with its 19 V/us typical slew rate, say 20 V/us, and up to 40 V power rails just to be safe, with a 4 Ohm load) would be:

qty (3) 68 uF capacitors, minimum, per rail,

assuming 30 nH total parasitic inductance for each cap and its connections to the power and ground pins. Remember, too, that the three decoupling capacitors should not share the same conductors, to connect to the power and ground pins, since that would make the total inductance not divide by the number of capacitors.

Of course, on the same board, there would also need to be "bulk capacitors" on each rail, totaling at least as much capacitance as the decoupling capacitors, and having low equivalent series inductance. The bulk capacitors are needed to recharge the decoupling capacitors between transient events. We might have to worry about low-frequency resonances, if the bulk capacitors are much larger in size than the decoupling capacitors. But if there is much ESR in the capacitors at the lower frequencies, it should help to damp any resonances.

Cheers,

Tom

Last edited by gootee; 6th December 2011 at 05:41 AM.
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Old 6th December 2011, 11:43 AM   #225
marce is offline marce  United Kingdom
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Another good reference:
http://www.interferencetechnology.co...ia/ITEM_01.pdf

PCB inductance:
http://www.polarinstruments.com/supp...ts/IPC1999.pdf

Most if not all published figures for PCB inductance are based on a ground plane being present, as the return path is critical in calculating inductance.

I'm currently on pages 436 onward of Mr Otts book as we are looking into planar capacitance and whether we use to many power islands as shown in figure 11.22...or whether a uninterupted plane pair with planar capacitance would be better.

Last edited by marce; 6th December 2011 at 11:54 AM.
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Old 6th December 2011, 11:51 AM   #226
AndrewT is offline AndrewT  Scotland
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The flow and return paths are equally effective in resisting flow of current.
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Old 6th December 2011, 11:56 AM   #227
marce is offline marce  United Kingdom
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Yes but inductance is probably the most important, especialy as speed goes up, and inductance has to ttake account of the return path, trace resistance is a minor consideration for decoupling providing there is adequate copper for currents required.
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Old 6th December 2011, 12:05 PM   #228
AndrewT is offline AndrewT  Scotland
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the effective inductance of the circuit, as seen by the load, must take account of both the flow path and the return path. Neither is more or less important than the other.
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Old 6th December 2011, 12:45 PM   #229
marce is offline marce  United Kingdom
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I am aware (very) aware of the impotance of the return path, but to calculate the inductance of a trace without a ground plane is more complex, inductance is of the loop, and with decoupling of digital signals or for RF decoupling the inductance loop is of paramount importance, you cannot calculate a PCb trace inductance without taking into account the return path, and if you dont have a ground plane the calculations are harder and the trace inductance will be higher. So for star grounded layouts as you often do on the amplifiers you realy need to use a 3D field solver such as those from polar intruments or simple calcs can be done using one or two of the options in the calculator before. The figure Gootee quoted is for a microstrip trace.
Inductance Calculator
http://www.speedingedge.com/PDF-File...ance%20(2).pdf

Just out of interest I am also collating inductance figures for small (0603-0402) chip capacitors and there routing, as with moving to HDI (high density interconnect) we can halve the inductance for a placed and routed 0402 capacitor.
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Old 6th December 2011, 02:10 PM   #230
gootee is offline gootee  United States
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I'm sure that I made a lot of wrong assumptions and some errors. Still learning.

Yes, all of those calculations (above) are probably quite optimistic unless a ground plane is used.

With a one-sided PCB, probably the best we could do would be to put two traces as close together as possible. And even then, the characteristic impedance (sqrt(L/C)) won't get below a hundred Ohms. e.g. Two flat conductors, .0027 inch thick, each 0.020 inch wide, separated by 0.04 inch, on a glass-epoxy PCB, would have a characteristic impedance of 120 Ohms. For our power distribution loops we would rather have 1 Ohm or less!

And THAT'S one reason that we need decoupling capacitors. They make a power/ground pin pair see a low impedance supply of current.

Also note that without a low-impedance DC power rail, the voltage noise induced across the power rail impedance by time-varying current demands could feed into the amplifier input, which could cause oscillation. (Imagine a simple transistor amplifier and the resistors from rail to transistor base and base to ground. Power and ground rails are coupled to amplifier input, there.) So we basically need to provide a short circuit for AC from rail to ground, across the entire band at which the amplifier has gain, to avoid having voltage disturbances feed into the amplifier's input. Our decoupling capacitors should also provide that. That's also another good reason to use a low-pass input filter, if the amplifier has gain at frequencies past what we need.

I still need to do some more learning, and simulations and experiments, to better understand how we might be able tio apply these types of concepts and calculations to simple DIY configurations.

I am hoping that someone who already knows will jump in. I'm already imagining having to arrange and solder a dozen small electrolytic decoupling capacitors like the pistons in a twelve-cylinder radial aircraft engine and then solder two leads from the assembly to my board.

Last edited by gootee; 6th December 2011 at 02:16 PM.
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