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Old 20th November 2011, 04:24 AM   #211
gootee is offline gootee  United States
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I guess maybe part of the question is about how many amps per second a real capacitor can give, initially, and then how long it can sustain that current-flow trajectory.

Just to try to put some ballpark numbers to it:

The magnitude of the maximum rate of change of a voltage sine wave is:

slew rate max of sine (in volts per microsecond) =

[(2 x Pi) x (freq in Hz) x (amplitude in volts)] / 1,000,000

So, for example, for a 60 V p-p sine at 20 kHz, the maximum slew rate would be about 7.54 Volts per microsecond, which occurs at the zero-crossing.

If the voltage is across a resistive load, the current amplitude would be the voltage amplitude divided by the resistance. So for the case above the current would also be a sine, of 7.5 A p-p. The maximum slew rate for a sine of that amplitude at 20 kHz would be about 0.94 Amps/usec.

So 0.94 Amps/usec, or maybe double that, should be about as fast as an 80-Watt amplifier should have to be able to change its output current, with an 8 Ohm purely-resistive speaker. So let's say 2 Amps per microsecond in order to be able to reproduce up to about 40 kHz, at that amplitude and with an 8 Ohm purely-resistive speaker load.

I guess that, at that rate, a lot of types of electrolytics might exceed their ripple-current ratings after 3 or 4 us.

-------------------

So what makes a smoothing or bypass capacitor release current at the precise time that it's needed? What makes a charged capacitor release current, in general, in the presence of an external voltrage across it? The external voltage must drop. I noticed in my simulations that small downward changes in the voltage across a large capacitor would be accompanied by relatively large flows of current.

In theory, a capacitor's current is the capacitance multiplied by the time rate-of-change of the voltage across the capacitor. But in my simulations (which I am quite sure do solve the differential equations correctly), the non-ideal capacitors generally didn't have enough time to react in order to conform to the ideal capacitor differential equation. What I "measured" from the output plots was that whenever the voltage had a transient downward blip of magnitude "delta V", then the magnitudes of the current pulses from the large electrolytic caps were about (delta V) / ESR.

And that makes sense, because that would be the maximum discharge current given by the solution to the capacitor equation, at time = 0 (assuming the ESR is the only resistance in the discharge path), and the times involved here were only long-enough for the cap to start trying to discharge and ramp quickly up to its maximum discharge current after 2 or 3 us, but then the voltage differential across the cap would go back to zero and so would the current. For example, in my simulations a temporary drop of the voltage by 70 mV would produce a capacitor output current pulse with a magnitude of about 2.3 Amps, from a capacitor with an ESR of 0.03 Ohms.

So I answered one of my own questions: The initial discharge current of an ideal capacitor does not depend on the capacitance. It is merely (roughly) the sudden change in the voltage across the capacitor divided by any nearby series resistance in the circuit.

I still don't quite know exactly what determines how much time it would take for a non-ideal capacitor to change its current from zero to the initial discharge rate that is called for. I'm guessing it involves the parasitic inductance.

Last edited by gootee; 20th November 2011 at 04:44 AM.
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Old 20th November 2011, 09:18 AM   #212
AndrewT is offline AndrewT  Scotland
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Quote:
Originally Posted by gootee View Post
And that makes sense, because that would be the maximum discharge current given by the solution to the capacitor equation, at time = 0 (assuming the ESR is the only resistance in the discharge path), and the times involved here were only long-enough for the cap to start trying to discharge and ramp quickly up to its maximum discharge current after 2 or 3 us, but then the voltage differential across the cap would go back to zero and so would the current. For example, in my simulations a temporary drop of the voltage by 70 mV would produce a capacitor output current pulse with a magnitude of about 2.3 Amps, from a capacitor with an ESR of 0.03 Ohms.

So I answered one of my own questions: The initial discharge current of an ideal capacitor does not depend on the capacitance. It is merely (roughly) the sudden change in the voltage across the capacitor divided by any nearby series resistance in the circuit.

I still don't quite know exactly what determines how much time it would take for a non-ideal capacitor to change its current from zero to the initial discharge rate that is called for. I'm guessing it involves the parasitic inductance.
I am following you intently.
You are one of a few that majors on current capability.
Cordell talks of current slew rate and current clipping as well as the conventional voltage slew rate and voltage clipping.

I agree that the "size" value of the current spike supplied by a capacitor is not controlled by the capacitance value.

The duration of that current spike is determined by the value of capacitance.
That's precisely why HF decoupling must be right next to the main current consumers in the very shortest tightest loop possible.
The MF decoupling can tolerate a bit more in the way of resistances/impedances and so they are located next on a slightly longer loop.
The smoothing in the PSU is the LF decoupling (that's a new term from my fingers) can be located much further away. Some even put them in a remote chassis.
Look at Peter Daniel's implementation of his chipamp. HF decoupling at the chip. MF decoupling on board a little further away. LF decoupling dispensed with completely. The result is his claim that this gives superb mid & treble performance. It is obvious that he follows the instantaneous current demand/supply philosophy.
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Old 20th November 2011, 09:27 AM   #213
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In a CLC circuit the inductor is also capable - very capable - of producing a high energy pulse.
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Old 20th November 2011, 10:17 AM   #214
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Old 20th November 2011, 02:00 PM   #215
gootee is offline gootee  United States
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Quote:
Originally Posted by AndrewT View Post
I am following you intently.
You are one of a few that majors on current capability.
Cordell talks of current slew rate and current clipping as well as the conventional voltage slew rate and voltage clipping.

I agree that the "size" value of the current spike supplied by a capacitor is not controlled by the capacitance value.

The duration of that current spike is determined by the value of capacitance.
That's precisely why HF decoupling must be right next to the main current consumers in the very shortest tightest loop possible.
The MF decoupling can tolerate a bit more in the way of resistances/impedances and so they are located next on a slightly longer loop.
The smoothing in the PSU is the LF decoupling (that's a new term from my fingers) can be located much further away. Some even put them in a remote chassis.
Look at Peter Daniel's implementation of his chipamp. HF decoupling at the chip. MF decoupling on board a little further away. LF decoupling dispensed with completely. The result is his claim that this gives superb mid & treble performance. It is obvious that he follows the instantaneous current demand/supply philosophy.
AndrewT,

Thanks. I was beginning to wonder if this thing was on or not, or if I was alone, here. But, in this, compared to Cordell and Daniel (and many others here), I am like a child... or only an egg.

I worry that maybe this angle is not even well worth pursuing and was hoping that someone who has already investigated it would jump in with some enlightenment. (Or maybe this is all just the most recent skirt passing by in the crowd that I randomly happened to notice.)

It "seems" like it would be very helpful to be able to actually quantify the capacitance requirements and characteristics, and quantify the effects of decoupling cap parameter changes (in terms of the capabilities and limitations of the output's reproduction fidelity). [Edit: (Engineer may be starting to wake up a little: ) We can break this down and first define the ideal current behaviors and requirements without thinking about capacitors. Then we could express how those might be able to be produced or satisfied, ideally and then in reality.]

I worry about transient reproduction accuracy, and "believe" that it's very important to be able to reproduce all of the Fourier components with the correct amplitude and phase. Otherwise, edges could become blurred, or exaggerated, or otherwise distorted, et al. This might all be merely "chasing the last 0.1% improvement" but that seems to be one reasonable definition of hi-fi.

Maybe it will make things clearer to me if I start from the other end of the spectrum and try to see what the absolute bare minimum capacitance requirements would be, under varying conditions (power levels, signal types, etc), and why.

I am pretty sure that the equations for the ideal case will be quite simple. Thirty years ago I probably could have had a complete closed-form solution within a few minutes. I deeply regret having allowed myself to gradually spiral down from deft to inept, in this area.

I'll do some more research and thinking, and will hope to be able to report back with more than just whining.

Cheers,

Tom

P.S. I wonder why no one markets some type(s) of "multi-capacitor" packages that would fit neatly right across device power pins and contain a continuum of capacitance with an optimal geometry for decoupling/bypass, with a range of models for different applications or for frequency ranges of interest (or whatever the criteria should be). Or why not have easily-stackable packages so one could "roll their own" and still get the best-possible geometry? And why isn't there a single package containing the ubiquitous "10uF || 0.1 uF" with an optimal geometry?

Last edited by gootee; 20th November 2011 at 02:27 PM.
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Old 20th November 2011, 05:00 PM   #216
marce is offline marce  United Kingdom
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Hi Gootee,
yes I agree we do agree
Regarding cappacitor supplying power, there is a good reference on this in one of Xylinx Virtes 4 or 5 data sheets. Though digital based it covers the same concept, providing power to supply instant current requirement for switching, while the main PSU reacts.
Any capacitor would (within reason) do the job if it was just capacitance that was to be considered, but the series ESL is the problem. That is why small physical lower value packages are placed next to the device pins, as the parasitic inductance is low they can supply the almost instantaneous requirement for current, then moving further away from the device power pins the larger reservoir caps, supply the next current requirements, then the power supply output cap(s), then finaly the voltage regulator, this being the slowest to react.
I will dig out the app notes etc I have on this when I'm back a work.
On local bypassing of large capacitors, I cannot find any designs that I have worked on where it has been done, on any power supply! it is not common practice (in the other world)
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Old 20th November 2011, 05:06 PM   #217
marce is offline marce  United Kingdom
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Again,
there are multicap packages available, these are quite often BGA or other small form factor SMD package, or there is the proadlizer:
http://www.nec.co.jp/techrep/en/jour...n01/090116.pdf

Again it is package size that dictates the effectiveness of a given cap value, so you can find 1n 10n combinations and 10n 100n combinations.
For digital designs the best method is closely coupled power and ground planes (sub 0.05mm dialectric) to give planar capacitance across the planes.
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Old 20th November 2011, 07:52 PM   #218
Elvee is offline Elvee  Belgium
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Quote:
Originally Posted by marce View Post
Hi Gootee,
yes I agree we do agree
Regarding cappacitor supplying power, there is a good reference on this in one of Xylinx Virtes 4 or 5 data sheets. Though digital based it covers the same concept, providing power to supply instant current requirement for switching, while the main PSU reacts.
Any capacitor would (within reason) do the job if it was just capacitance that was to be considered, but the series ESL is the problem. That is why small physical lower value packages are placed next to the device pins, as the parasitic inductance is low they can supply the almost instantaneous requirement for current, then moving further away from the device power pins the larger reservoir caps, supply the next current requirements, then the power supply output cap(s), then finaly the voltage regulator, this being the slowest to react.
Thinking in the time domain can be dangerous and misleading if you are unable to actually visualize the differential equations.
Maybe some people can do it, but I honestly cannot.
Compensating the connections inductance to the reservoir capacitors with a small, local capacitor looks like a good idea, but unfortunately, the solution of such a system is oscillatory, meaning in fact a resonance peak in the frequency domain.
Servoed electronic supplies displaying a delay in the reaction when a voltage drop appears at the output are in fact gyrators, ie synthetic inductance and have the same kind of problems.
Which is why high performance regulators have difficulties tolerating perfect capacitive loads at their outputs.
The problem is always the same, and is mainly incorrectly addressed, because people are unable to think vectorially in the time domain, and unwilling to think in the frequency domain.
In the frequency domain, only the module is important, and even if you are vectorially challenged, like myself, ie unable to think in multiple dimensions simultaneously, you can get away with it.

Compensating a reactive element with the opposite reactive element looks like a good idea until you realize this works at one, and only one frequency: the resonance.
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Old 21st November 2011, 11:43 AM   #219
marce is offline marce  United Kingdom
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Luckily there is cool software that does a lot of the work, and provides pretty liitle pictures, in my case this:
http://quadrasol.co.uk/useruploads/f...2011_10_05.pdf
Trouble is the software isn't cheep (my complete PCB design system cost 10K a year in maintenance alone!!), but when you have a few 700,800+ pin devices on a board, plus memory plus analogue, plus audio out etc you need the kit.
As the guy who teaches people how to use the software says, you dont have to know the maths, thats what computers are for...
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Old 21st November 2011, 07:17 PM   #220
AKN is offline AKN  Sweden
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Hi marce,

Thanks for linking to that pdf. Very interesting!
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