Asus Essence STX Extension Oustide The Case?

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Listening. It's very evident. Nothing subtle about it.

If it isn't subtle then you should be able to easily measure it!

As it happens the Xonar uses an internal PLL within the Cmedia chip to generate its on board clocks.

From my own measurements I have a feeling that the Xonar might only bring in the PLL for frequencies at multiples other then the frequency of the main crystal. So for 192/96/48 etc it uses clock division of the main crystal. I am only basing this on my own jitter measurements in loopback though, so this could be full of holes.

44.1 on the left 48k on the right. Interestingly this problem goes away when comparing 88.2 and 96kHz, but it's reason enough to upsample using software imo. This was done using ASIO drivers.

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Using a better external clock might improve the 48kHz performance, but I don't know if it would do much if there's a PLL after the clock.
 

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For a digital clock, the most critical part of a digital circuit...
How can you tell by listening how the clock is performing, clock signal integrity is affected by a whole host of things, PSU, decoupling and most of all the length of the track and any impedance mismatches, removing an on board clock and running a wire to a pad is one of the worse mods I can imagine.
But you cant examine the clocks waveform by listening, not examine any other possible integrity issues created by messing about with clocks. You need scope shots and preferably a network analyser. Clocks being the most critical part of a digital circuit are laid out to minimise the trace length, and more often than not a series resitor is used to match the output to the trace impedance to minimise ringing and overshoot, you need the right tools to do this, it is in the digital domain.
Posr #41 shows how to do it...
 
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