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#1 |
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diyAudio Member
Join Date: Jan 2012
Location: Nottingham, UK.
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Hi,
I've been working hard creating a quad SDPIF output cape for the BeagleBone for use with my Meridian DSP speakers. That should be available by the end of Feb after I have sorted out the software side of things. I now have bigger aspirations! So I am about to embark upon a fairly huge project and would like the input of my fellow DIY'ers. I want to design a open source AV computer based on the Texas Instruments Davinci series of DSPs, in particular the DM8148. The AV computer would have 1). HD video expansion slots for HD input and output (HDMI, SDI etc) 2). Five audio expansion slots (access to 4 or 5 stereo i2s channels). 3). PCIe x4 slot (x1 electrical for DVB tuners etc). 4). USB, SATA, LAN and Firewire The broader community could design and build enclosures and expansion boards for use in the computer such as pre/power amps, DACs, inputs, outputs, crossovers etc. Something along the lines of... ![]() I welcome your thoughts and ideas. David. |
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#2 |
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diyAudio Member
Join Date: Apr 2005
Location: Pilsen
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How do you plan to synchronize the input and output clocks?
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#3 |
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diyAudio Member
Join Date: Jan 2012
Location: Nottingham, UK.
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The six McASP units on the DM8148 are very flexible. Each unit has its own transmit and receive clock that can be independently programed. You can synchronize with a system wide internal master clock or high quality external and divided down.
For example McASP0 could use the internal master clock with McASP1-5 configured as slave and sharing the clock. Or alternatively a high quality external clock that can be divided down depending on the transmit/receive requirements. Whether or not TI have the software finished to do all this is another matter entirely. Community users would have to submit patches to get McASP working, I think. Last edited by sgpu; 3rd January 2012 at 01:42 PM. |
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#4 |
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diyAudio Member
Join Date: Apr 2005
Location: Pilsen
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What I meant is when the incoming digital signal (HDMI/SDI input) generates the master clock for the chain. But I guess your planned hardware can run in such a mode since you have all aspects of the hardware under control.
Last edited by phofman; 3rd January 2012 at 02:15 PM. |
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#5 |
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diyAudio Member
Join Date: Sep 2007
Location: Hangzhou - Marco Polo's 'most beautiful city'. 700yrs is a long time though...
Blog Entries: 46
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Not wishing to throw any cold water in your direction but one of the greatest challenges to getting a really clean hi-end sound is freedom from RF noise - your proposed computer does seem to have the potential to be almost as noisy as a current Intel-based PC. Which might be fine if its purely a digital device - so do you intend to have analog outputs?
__________________
I think ideas are what you want to get rid of. I don't really like songs with ideas. - Leonard Cohen |
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#6 |
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diyAudio Member
Join Date: Jan 2012
Location: Nottingham, UK.
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No need for the cold water, it's raining here! RF is our nightmare but somewhere along the line you have to compromise on noise. The audio is digital up to the expansion connectors. The onus would be on the expansion board designers to keep their noise down if they chose to go analogue in any way.
We would have to come up with the expansion specification with as clean power as we can provide (within reason). This is something for PCB designers to lose sleep over. :-) |
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#7 |
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diyAudio Member
Join Date: Apr 2005
Location: Pilsen
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Another point - PLLed clocks vs. clean crystal based for audio I2S.
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#8 |
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diyAudio Member
Join Date: Jan 2012
Location: Nottingham, UK.
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The DM8148 can have an optional 20Mhz external oscillator for the system clock and a, say 27Mhz, for the A/V subsystems (Video, Audio, HDMI, etc). Even so, there is a PLL cascade on-chip to distribute the clocks.
If anyone is interested you can read about that here (section 2.3) http://www.ti.com/litv/pdf/sprugz8 Last edited by sgpu; 4th January 2012 at 09:04 AM. |
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#9 |
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diyAudio Member
Join Date: Apr 2005
Location: Pilsen
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#10 |
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diyAudio Member
Join Date: Jan 2012
Location: Nottingham, UK.
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I think there is the option to bypass the internal PLL and provide a clock directly to the McASP modules (MCASP_AHCLKX?) too. That could improve i2s input/output clocking, maybe.
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