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Old 20th January 2012, 11:55 AM   #41
marce is offline marce  United Kingdom
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What I always use as part of my manufacturing instructions is the paragraph on how they should process my solder mask, in the attached PDF file.
This gives the manufacturer room to get the best yield whilst preventing exposed copper.
Attached Files
File Type: pdf Solder Resist.pdf (8.2 KB, 32 views)
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Old 20th January 2012, 06:39 PM   #42
sgpu is offline sgpu  United Kingdom
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Thanks Marce.
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Old 20th January 2012, 09:53 PM   #43
sgpu is offline sgpu  United Kingdom
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I could consider arranging for a third party to design in the ADV7612 as a 1 or 2 port HDMI (audio only, no hdcp) receiver add-on board. The output from this device supports TDM8 channel so would not take too many resources from the main board.
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Old 25th January 2012, 01:51 PM   #44
sgpu is offline sgpu  United Kingdom
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I've just about finished modifying the EVM schematics. Is there any particular pins anyone would want on any of the audio headers?

I'm heading in this direction.
http://www.lucidchart.com/publicSegm...55e2/image.pdf
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Old 27th January 2012, 09:07 AM   #45
sgpu is offline sgpu  United Kingdom
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Has anyone come across any GStreamer crossover elements/bins? It strikes me that GStreamer would be an ideal way to create whatever open source cascade/transform you would care to design. You could build a crossover pipeline with a graphical gui (gstedit for a start) if the elements and bins were available. A bit like this DVD playback pipeline..

http://www.cin.ufpe.br/%7Ecinlug/wik...Gst-editor.png

I may consider writing GStreamer elements for my project that harness the C674x DSP attached to the Cortex-A8.
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Old 1st March 2012, 09:45 PM   #46
sgpu is offline sgpu  United Kingdom
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I have been busy working on a n-channel GStreamer audio sink.

SINK -> 31-band PEQ per channel -> multi way XO per channel -> McASP i2s or DIT PCM. I am developing a node based UI for the XO and i2s configuration so that users can build whatever chain they wish to any number of i2s outputs.

The sink uses a GstAdaptor to fill up buffer 2ms of audio frames to be processed by the DSP. The node tree created by the XO UI is used to build the crossover from the available DSP blocks that I am developing. It will require some work to get the pipeline working properly and latency low.

The 31 band EQ with all bands active currently uses 23MHz DSP (4% utilisation) for a stereo 44.1kHz stream. Quite a bit still to do to optimize the biquad stages and register management.

Hardware schematics and PCB are well under way for the mainboard. I should have something substantial to share later in March.
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Old 4th March 2012, 09:54 AM   #47
marce is offline marce  United Kingdom
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Hi SGPU,
I am still watching the thread, not been as active recently as I have been changing jobs, so the last month has been murder, start the new job tommorow!
Keep up the good work.
Marc
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Old 5th March 2012, 10:32 PM   #48
sgpu is offline sgpu  United Kingdom
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Thanks! I have the double precision stereo 31 band PEQ down to 52k cycles (all bands active) for a 1ms buffer (48kHz). Each channel has independent PEQ. The use of "restrict" type in certain areas really brought down the cycle count. I am now trying to shoehorn my PEQ into a DSP accelerated gstreamer element ( https://github.com/felipec/gst-dsp is quite useful ) that outputs directly to McASP from the DSP side.
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Old 6th March 2012, 11:55 AM   #49
qusp is online now qusp  Australia
Sometimes a square peg fits a round hole just fine
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been watching this since the beginning, very interesting project and a lot of work. cant wait to see it all come together. how are you thinking to package the sale Mobo fully populated and with a minimum audio module and sync package?
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Old 6th March 2012, 07:05 PM   #50
sgpu is offline sgpu  United Kingdom
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In terms of software support I'm creating a layer for Angstrom Distribution with my changes and a few custom recipes. I picked up the TI EVM last week so I can really start work in earnest now.

Amongst my many tasks
- trying to figure out the McASP initialization and setup on the DSP side and how I can switch between i2s and DIT per serializer and also data direction.
- selection of a good 20Mhz system clock.

In terms of hardware the board will be fully populated. I expect to have a breakout board for i2s and SPDIF at the time of release.
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