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Old 4th January 2012, 11:21 AM   #11
sgpu is offline sgpu  United Kingdom
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Expansion board makers could chose to use the clock generated by the main board PLL or if they wish they can create a master clock themselves and send that clock to the McASP module. For example if you wanted 8-ch ADC inputs you could have a PCM4220 with a high quality master clock and slave 3 more PCM4220 and also slave the McASP. The same could be done for DAC outputs, I think. There are definitely some options in terms of cystal use as opposed to the on chip PLL. I will check a few things with a TI technician.
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Old 4th January 2012, 11:30 AM   #12
phofman is offline phofman  Czech Republic
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Quote:
Originally Posted by sgpu View Post
Expansion board makers could chose to use the clock generated by the main board PLL or if they wish they can create a master clock themselves and send that clock to the McASP module. For example if you wanted 8-ch ADC inputs you could have a PCM4220 with a high quality master clock and slave 3 more PCM4220 and also slave the McASP. The same could be done for DAC outputs, I think. There are definitely some options in terms of cystal use as opposed to the on chip PLL. I will check a few things with a TI technician.
Sounds good
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Old 4th January 2012, 12:04 PM   #13
marce is offline marce  United Kingdom
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Layout would be fun, especially as its an 0.8mm pitch BGA, so it will require a few layers. Nearest I have done is a VC5510 feading 8 codecs (TLV320AIC33) with FPGA controller, 3 gnd/pwr pairs for all core voltages etc, 4 sig/gnd pairs for most signals, and top and bottom layers (had other bits and pieces on board as well). On reflection it would have been cheaper and better electronicly as a HDI PCB layout.
Another interesting aspect will be the mechanical aspect of the daughter boards and type of connectors used. Will certanly be an interesting design.
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Old 4th January 2012, 12:17 PM   #14
sgpu is offline sgpu  United Kingdom
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Quote:
Originally Posted by marce View Post
Layout would be fun, especially as its an 0.8mm pitch BGA, so it will require a few layers. Nearest I have done is a VC5510 feading 8 codecs (TLV320AIC33) with FPGA controller, 3 gnd/pwr pairs for all core voltages etc, 4 sig/gnd pairs for most signals, and top and bottom layers (had other bits and pieces on board as well). On reflection it would have been cheaper and better electronicly as a HDI PCB layout.
Another interesting aspect will be the mechanical aspect of the daughter boards and type of connectors used. Will certanly be an interesting design.
I was considering reversed PCIe x1 slots for audio expansion and reversed x4 slots for the video/audio expansion. Each slot would carry clocks, data and power and various buses.

Last edited by sgpu; 4th January 2012 at 12:29 PM.
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Old 4th January 2012, 12:18 PM   #15
sgpu is offline sgpu  United Kingdom
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I believe McASP can be used like this but will be checking it with TI.

Click the image to open in full size.
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Old 4th January 2012, 01:51 PM   #16
sgpu is offline sgpu  United Kingdom
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Pin mux proving to be an issue too.
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Old 4th January 2012, 02:14 PM   #17
marce is offline marce  United Kingdom
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I was wondering whether a connector pair combination would make the design of add on cards easier, it avoids having the PCIe fingers gold plated and the quite complex board outline, similar say to VME with DIN connectors.
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Old 4th January 2012, 02:20 PM   #18
sgpu is offline sgpu  United Kingdom
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Good plan, a back plane kind of connection could work well.
Something like the right angle Samtec Searay connecting to an upright socket on the main board.
http://www.samtec.com/documents/webfiles/current_literature/searay.pdf

Marce: Solidworks huh? Same here!

Last edited by sgpu; 4th January 2012 at 02:33 PM.
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Old 5th January 2012, 11:19 AM   #19
sgpu is offline sgpu  United Kingdom
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What is your opinion on using cmos clock buffers? Say I wanted to distribute a 24.5760 audio master clock to the expansion ports, what would be the best way to do that? I have been looking at devices like

http://www.datasheetcatalog.org/data..._datasheet.pdf
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Old 5th January 2012, 12:10 PM   #20
marce is offline marce  United Kingdom
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I'm off sick at the moment so dont have access to my full data bases, but just recently we have done a lot of work on clocks (especialy the JTAG clock (25Mhz so similar frequency) that gets distributed to quite a few devices, 5+) using Cadstar SIV (signal integrity verify), the results confirmed with actual boards. We used a bespoke clock driver IC's, CDCV304PWR and CDC2351Q with both a series source resistor and AC parallel termination at the reciever (resitor with a small value cap). The values where chosen using the simulation software to match the actual physical layout. This is quite time consuming but we now simulate ALL cloaks and critical nets as its quicker less error prone than guesswork. I also have some notes from our boundry scan equipement providers on clock distribution, again I wont be able to get to them for a week.
The device you have chosen again should work, but on a motherboard based design such as this I would look at simulating the clock from the source, through the motherboard traces, through any chosen connector system to the actual daughter board. In Cadstar SIV you can model connectors and interconnects as well as the on board traces. As both the clock and other signals to the daughterboards are going to be critical as part of the design spec, providing a basic daughterboard design with a bus interface would be benefitial, as any daughterboards added will have the same front end. Again similar to other bus systems, giving the advantage of knowing the effect of added daugter boards on the systems operation, and making it easier for others to create their own addon boards.
The other problem with a motherboard based system is also the mechanical support of the the daughterboards. Using a 19" rack system would be overkill and rather expensive for DIY, but got back to thinking about PCi and small form factor PC cases, these are quite cheap thesedays and all the dimensions are well specified. Again the only caveat is that the PCB's tend to be a bit dearer as you have to have the PCIe fingers hard gold plated. A look through SCAN and CPC, RS at cases to find a cost effective and easily implemented solution for home construction, and a look through connectors like Samtec and Molex is a good idea. I have been looking at quite a few connection solutions recently (fed up off the things) as we do a similar thing, but our first choice of connector failed ballistic shock tests, not a problem for home use unless you have ballistic kids running round. Some of my favorites for good signal integrity are the ones with an integral solid ground. Again for home design through hole would be easier and more rugged, though we are using surface mount down to 0.5mm pitch in harsh situations, but soldering has to be spot on as this is the only mechanical fixing for these types of connector, and the boards do require other mechaical support.
Sorry rambling on, just thinking as I write
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