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Old 3rd September 2009, 11:47 PM   #11
dmills is offline dmills  United Kingdom
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Join Date: Aug 2008
Location: High Wycombe
Originally Posted by SunRa View Post
I would really like to know if these PCI card are bit perfect.. From what I've read so far, all of them seem to have a PLL recovery scheme, in which the Master clock is the PC. The correct implementation would be the master clock in the dac, and the PC should be slaved... But again, I don't have a good understanding of these architectures either..
Not in any card I am familiar with!

The usual model is that the PCI interface loads its shift register from a buffer that is refilled by triggering a DMA cycle on the PCI bus. The shift register is clocked out by the on card crystal (often using a PLL to derive the appropriate clock rate from a single rock).

This is certainly how most of the ICE1712 based things work (some have additional PLLs to deal with locking to things like SPDIF inputs, but that is a detail.

As MCLK always has to be supplied to the converter chip from an external source, I don't see how you easily improve on this arrangement (other then possibly by upgrading the entire clock generation scheme to avoid using a crystal referenced PLL as the master clock (use two rocks instead with good quality divider chains, but it would be a lot of faffing about)).

Nothing I am aware of uses any of the various clocks available on the PCI bus as a clock source for the converters.

Regards, Dan.
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Old 4th September 2009, 01:40 AM   #12
SunRa is offline SunRa  Romania
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Join Date: Aug 2004
Location: Romania
Thanks for clarification Dan,

So that means that basically if I settle to one sample rate (say 192Khz) and I put a good clock, a good output stage and feed all this with a good PSU, I should be done ..

I really have to get myself one of the new sound cards.. I think I just delayed the moment hoping some USB based miracle to happen... (asynchronous if possible )
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Old 4th September 2009, 05:08 AM   #13
phofman is offline phofman  Czech Republic
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Join Date: Apr 2005
Location: Pilsen
Ice1712/24 cards do not use jittery PLL for clock generation, but two crystals. The driver is responsible for setting the chip's internal clock dividers according to current sample rate. Cards with external clock scheme provided by Xilinx CPLD (Juli, Infrasonic Quartet) do not use the internal dividers, but dividers are programmed in the CPLD and the driver instructs the CPLD via GPIOs of ice1724. From the clock POV it is virtually the same, the Xilinx setup provides independent clock for reliable detection of SPDIF input sample rate, and the card can output 176,4kHz on SPDIF output unlike internally-clocked ones (probably a bug in ice1724).
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