Lovoltech name change

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So, I wrote the "Mike@qspeed" :D Does that mean they will answer e-mails now??? I've called Lovoltech, they don't answer the phone??? Besides the infamous uses in ZV9, I "currently" work in SMPs applications and they don't seem to need to answer my questions or live up to their claim of providing Pspice models on request from that angle either? It apears the general JFET Pspice model will not follow the low voltage, low current "triode" characteristics of their devices:bawling: :bawling: :bawling:
Nelson, is it possible your reliable source could help us modelers out???
I don't even have a kitchen table now :bawling: :bawling: :bawling:
 
Nelson Pass said:
My projections for the probable market for power JFETs did
not make a dent in their business model.

It did not make a dent...it was TOTALED!

I guess your competitors are still trying to figure out where the heck is the Jfet sweet spot this Pass guy is talking about. Once they do, it's already Jfet famine.
:bawling:
 
Well, I'm happy to say, Mike @qspeed responded very quickly:D :D :D Shattering all my claims in the above post :xeye: Thank you Nelson!
I don't have to much time till next week but, for you Pspice modelers, I would imagine I am free to diseminate them in good faith to anyone who has also been fiddling with a ZV9 in Pspice. Or maybe you would like to extract their parameters for your own Simm App :bigeyes: :bigeyes: :bigeyes: Of coarse I'm not sure, I havent looked yet, their model may not be usefull for that below 5Volt, below5 amp region either:confused: :confused: :confused: Just e-mail me and I'll forward them...
As far as dents, I tried to propagate the new parts throuout our SMPs org and only 1 engineer even responded :whazzat: Later we had a low voltage reg project we had great difficulty to figure out :confused: I went home and modeled the LU1014D into a prototype circuit and it worked just fine. However, for bis reasons, it really was not an appropriate solution in that instance... Oh well, I still have all my parts at least...
 
Nelson Pass said:
Lovoltech now goes by the name Qspeed, I am reliably
informed, and have just introduced a high current, high
voltage high speed soft recovery rectifier.

Have you had a look at the "new" SemeLab C3 ultra soft recovery diodes ?

Nelson Pass said:
My projections for the probable market for power JFETs did
not make a dent in their business model.

This is no surprise. LIS indicated that they would need to sell about USD 500K worth of devices per year in order to justify producing power JFETs, though that was a "rough estimate" for a complementary pair. Smaller foundries can make single runs for less, but expect insane lead times.

Perhaps it's time to "melt your own sand" ;)

Anyway, on a more serious note, you could try asking them for unpackaged chips in a carrier, or even an unprocessed wafer. There are several companies out there that will take care of testing, bin sorting and packaging for you, even in smallish quantities.

SemeLab, for instance, offers packaging services. This device would probably be pretty nice in a SOT227, TO3 or SmartPack capsule. Especially a dual, with the consequent improvement in thermal matching.
 
Nelson Pass said:
I am of the belief that Qspeed needs a lot more than $1M/yr
just to change the package, much less make a custom chip.

I was not suggesting that they make a custom chip.

Almost all manufacturers provide the chip inside their packages in unpackaged form, typically in a unit called a chip carrier (1000+ chips). This is so that companies can assemble them in multi-chip arrays, or attach them directly to circuit boards, etc. Usually, these chips cost less than the packaged equivalents.

Such a chip carrier can be shipped to a company that does packaging, in order to package it differently from what the company itself does.

Since the company itself is catering to a certain market, it will cost them a lot, for little gain, to do any changes, such as using a different package. For a company that does packaging for a living, however, that is where their money comes from: they package chips for many different clients.

Shipping an order in chip carrier form is probably something they already do, and something that shouldn't cost them anything.
 
suiraMB said:


Almost all manufacturers provide the chip inside their packages in unpackaged form, typically in a unit called a chip carrier (1000+ chips).

Such a chip carrier can be shipped to a company that does packaging, in order to package it differently from what the company itself does.


Looks like we'll see power jfets in TO-247s or even TO-3s(?) in Pass products soon, Nelson?
 
As someone who design production equipment for the semiconductor industry as a living for 20 odd years, including wire bonders, die bonders, wafer scanners, ...., I took the liberty to put in my 2 cents.

The likes of Loveltech, Semelab, Linear Systems, ... are, as far as I am correctly informed, so called fabless design houses. That means that have no production facilities of their own and only subcontract the entire production process to someone else, so called foundries. They design the product, be it transistor or else.

The major cost in making a new chip, other than design cost, is the mask set. For top of the line microprocessors, this can cost millions, even if you only want one wafer. For high power transistors, this is significantly less, but it still costs money. The typical writing time for a reticle from computer design data is 1 to 10 hours (E-Beam direct write).

If you only want one wafer, you can also e-beam direct write on wafer. This is what semiconductor companies do for their own prototyping, or how the US military make their own chips.

Packaging companies would then take the finish tested wafer, saw them into dies and package them -- silver epoxy them on a carrier (e.g. TO3P, TO3, TO220, ...) and then connect the circuit to the legs by wire bonding (or flip chip or .....). This involves some programming of the bonding equipment, but it is the least costly exercise. There are plenty of subcontractors in Asia for such processes.

Taking a standard LU1014 and packaging it in TO3 brings nothing extra other than cosmetics, as the thermal bottleneck is NOT the contact surface of the package to the heatsink (assuming you know how to do it right), but the contact surface between the die (which is MUCH smaller than the package) and the lead frame (the piece of metal than contacts the heatsink on the backside of the package).

So TO3 is in theory better than TO3P as it provides a slightly larger surface for thermal contact, but you are not really doing anything to the highest thermal resistance in the chain, which is inside the package.

The next issue is of course the wire bonding, which for large current devices are almost exclusively done with aluminium wires, as large diameter gold wire bonding is technically much more difficult and hence costly. I couldn't help laughing every time when people say how important it is to have silver connections everywhere, except they can't do anything to the chip, which is full of aluminium as interconnects.

But, I am sure Loveltech (or Linear Systems for that matter) will sell you a few wafers and you can, without too much extra cost, get them packaged in TO3 or TO3P or else.


Patrick
 
Wrt fabless companies:

I can't comment on Lovoltech, although it seems plausible, but I believe SemeLab does the foundry bits through their sister company, SemeFab. It is not entirely unlikely that they outsource large volume standard selection runs, though.

Wrt cost of chips:

As I understood it, the mask set for a 100mmØ power BJT wafer (5 masks) can be produced for as "little" as €2000 or so by one of the smaller companies. But, yes, wafers were quoted at <€100 each, with minimum quantities of 25 wafers, so the NRE costs dominate at these quantities.

For JFETs, I would assume you don't need as elaborate masks, though, unless you are doing SIT or somesuch?

Wrt e-beam direct write:

I've heard several universities use this approach for their prototyping work, so if one actually had a design, it would presumably be possible to use their services. I know the army sells their excess capacity to smaller companies for prototyping etc.

However, that is rather nontrivial, so what I was suggesting, was using the existing chips.

By the way, can one manufacture static induction devices with direct write technology? ISTR they were rather complicated to produce cost-efficiently.

Wrt packaging:

Yes, I realize that the die-to-frame surface is the limiting factor here. Oops. :angel:

However, there are options, such as better bonding, internally paralelling devices, using copper packages, etc., which should improve things somewhat. Also, a SOT227 can hold a fairly large number of paralelled devices, for example.

Wrt wire bonding:

Yes, well, I'd be inclined to agree. Though some companies seem to prefer aluminium over Cu/Au/Ag. I'm not sure what the rationale behind this, if any is. It does have higher sound propagation speed (some argue microphonics to be relevant), and is paramagnetic, as well as having a higher oxidation state than the other three (except Au).

Wrt custom packaging:

Do you think there are any options that would give any significant improvement in effective power handling, save for internally paralelling adjacent/matched/sorted chips?


It is nice to see someone with inside knowledge of these things chime in, thanks.
 
Hi,

I have work in semiconductor long time back so the info may be a bit outdated.

As I recall, we use only two kinds of wire, Aluminum and Gold wires.

There are two kinds of Wire Bonder that I know then which is called a ball bonder and wedge Bonder. Ball Bonder uses mostly gold wire as I recall but I could be wrong here as I did not work on them directly and wedge are using both which I did have work on them. Wire varies in size from 0.7 mil to 1.5 mil

For a higher power, two wire are used to bond the die to the frame, of course there will be enought space on the die metal pad to accomodate them.

Gold are normally use for product with higher spec/grade( MIL-Spec ).

There are also two ways to bond the die to the frame, one is the use of conductive epoxy or gold flakes.

With the above the use of Gold and alum would make sense which is more economical.

just my 0.2cent.

Cheers
unmibh
 
The only way to improve thermal conduction within the chip is to increase substrate area (if necessary larger than what the real transistor really needs to occupy) and do eutectic die bonding rather than silver epoxy (all known techniques). But that means less transistors per wafer, and hence cost. But one has to question whether it is necessary, just as one questions whether TO3 is necessary.

As to wire bonding, you can do gold wire up to a couple of mils (0.00x"), after that you have a hard time forming the ball with the E-torch. There are wedge bonders which can bond aluminium foils a few mm wide (I have seen up to 4mm) at room temperature. That is probably the preferred method of bonding high current devices.

If one really wants to go to the extreme of getting transistors made for Audio, I would vote for Power JFETs. Not Loveltech variants, but really power devices like the famous 2SK60's, etc. And then not do wire bonding but use flip chip (solder balls) instead. Personally I do not think it matters whether it is TO3 or TO247, as long as you use a good insulator (by that I mean not mica and not Sil-Pad).

The rest you can buy, so why bother.


Patrick
 
For a simple diyer like me with simple tools at hand (with a simple circuit), I'd rather have transistors that can be easily mounted on a flat surface heatsink with a silpad, a bolt, and big round washer:) Include easy termination of its leads as a big advantage.
 
package size

... I'd rather have transistors that can be easily mounted on a flat surface heatsink with a silpad, a bolt, and big round washer

I fully agree. The LU1014 has quite a decent thermal resistance junction to case of 1.8 °C/W, but compared to TO247 the surface area of it's package is smaller by more than an order of magnitude. Using the same standard mounting methods would give an accordingly higher thermal resistance for the smaller package, so I would still consider this to be the bottleneck.
 
Sure, except that a Sil-pad on a TO247 would give you a temperature drop of about 10 degC at say 1.5 amp (my experience anyway), and you might be able to improve that by say 2 degC changing to a TO3.

If you are prepare to get transistor custom packaged for a 2 degC improvement, you might as well spend the effort on getting a better thermal path from your transistor to the heatsink, at a fraction of the cost.

If you don't like the small thermal contact area of the LU1014, just solder a piece of copper on, like Peter Daniel did for his ZV9. That still does not solve the problem of the thermal resistance inside the chip. Which is why you HAVE to cascode the thing.

http://www.diyaudio.com/forums/showthread.php?postid=993974#post993974

That is, for example, NOT the case for a 2SK60.

A TO3 / TO3P / TO247 package has an internal thermal resistance of typically 0.8 K/W, for your reference. A Sil-Pad for such packages typically 0.3K/W.


Patrick
 
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