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Old 11th September 2006, 10:36 PM   #11
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Re-Hi, Graeme
Quote:
Originally posted by gl
Hi Cheff,

I have built a one channel proto but I have not yet powered it up. I have made corrections regarding the polarity of the SuSy connection based on your suggestion at the time. I really like the fact that you only had minimal offset.

I used mosfets only as followers. That was how I increased the output current. I noticed that you included current gain in your mirrors.


IMHO, as the following stage (the amp) has a high impedance, and hence a voltage input, you don't need a high output current. For its major part by far, the current running through the mirrors is shared by the upper and lower mirrors, and the difference of these upper and lower currents is going to ground through the lowest impedance path, i.e. the output resistor Rout, which converts the current to voltage...

Quote:
1) What bias current are you using in the JFETs and how do you set it? There is a lot of Idss variation in these parts and other people may have to tweak some values to make your circuit work with BL parts from different batches. The two pots you show seem to adjust only the relative and absolute offset.
The jfet bias current is roughly 3.5 mA/Fet, and it is set by the Fets' source resistors. It obviously depends on the Id=f(Vgs) curve, so Idss matters, but amongst the 6 modules I built, I didn't see huge variations of the bias current, despite of the different batches of BL I had... The important thing here is less the bias current than the transconductance that sets the first stage gain.

Quote:
2) Did you Vbe match the current mirror transistors? I did, but I don't know how important it is.
Sure, the mirror function is better achieved when Vbe and gain are matched for these BJTs, but honestly, I didn't investigate this issue, and really can't say how it impacts the sound.

Quote:
3) Why are the emitter resistors on the mirrors so large? It seems that this would limit the output swing. I have always understood that minimal values are best - with a voltage drop of only a few tenths of a volt. Note that I used 100 ohms here. Did you choose your values based on listening tests?
Well, I do not have my files handy, but if memory serves, the maximum output swing is around 30V peak to peak, but I'll check and report back. Nevertheless, count it in tens of volts, which is really sufficient for a linestage.

The mirror resistance is here to provide some gain, helping the first stage in order to get a higher open loop gain (around 35dB in simulations). Their values are on par with the drain resistors', with a rough current gain of 2 here. And if the resistor is too low, current will increase, and the dissipation in the output transitors will become too high, so I had to make some compromises between gain and thermal equilibrium. With values here, the current through the output BJTs is around 7mA.

As I stated above, I plan to investigate the effect of a higher emitter resistor (1K to 1K5), both on the sound and on the dissipation, as the output current will decrease. But I'd rather listen to music for the moment

Quote:
4) The 450/550 transistors on the output have a Vce max of 45V. It seems risky to run them off 24V rails. This is why I used the 696/796 pair.
With an output wing of +/-15V (must check), the max Vce will be 34V with a 24V supply, as the emitter resistors drop around 5V. Yes it's close, and it can be an issue if you push it to the limits, but in "normal" use, you don't need that swing. But I'd be interrested in knowing how higher voltage bjts behave compared to the ones I used. Another test...

Quote:
Once again, I really like your design. I have recently come up with a requirement for a UGS stage and you have inspired me to get back to work on it.

Cheers,
Graeme
Thanks, but you were part of my "intellectual" trip to get here

And I really hope you will soon have something working. The end's worth the journey. That's really the best preamp I ever had. May be I made some mistakes/compromises in designing it (please point them out, that's the way I learn), but as is, it's awfully wonderfull Really.

Best,
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Old 12th September 2006, 08:05 AM   #12
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Just checked the max output swing, and sims gave me a rough 25V peak to peak... Bad memory

So the ZTXs should be safe... And forget what I said about the 5V emitter voltage drop... Was too late to think properly

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Old 12th September 2006, 01:27 PM   #13
mlloyd1 is offline mlloyd1  United States
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cheff:

very interesting and thanks for sharing!
i like your design. i'm curious; any special reason you didn't want to use folded cascode?

mlloyd1
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Old 12th September 2006, 01:53 PM   #14
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Hi mlloyd1,

Thanks. And for sharing, thank Nelson

There's two main reasons I didn't use folded cascodes.

A psychanalytical one, as I always have been unable to have them properly functionning in any design I built with them, ugs or not... Mea culpa, haven't try hard enough, surely

A more practical one, as I needed a little more open loop gain which I guess I couldn't achieve with a mere folded cascode, or I'm mistaken...

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Old 12th September 2006, 02:18 PM   #15
gl is offline gl  United States
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Hi Cheff,

Thank you for the responses. Please keep us all up to date on any changes and improvements you make based on continued listening.

Regards,
Graeme
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Old 12th September 2006, 09:46 PM   #16
mlloyd1 is offline mlloyd1  United States
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cheff:

thanks. i was curious because i am trying to settle on a gain block to use for a "no-overall feedback loop" line stage. at this point, I've pretty much settled on the complementary diffamp jfet feeding complementary folded cascode bipolar transistors. high open loop gain is not a requirement for my needs. looking at the blowtorch discussion, i really wanted to try bipolars instead of mosfets on the back end.

maybe charles hansen will drop a pearl or two.

mlloyd1


Quote:
Originally posted by CheffDeGaar
Hi mlloyd1,

Thanks. And for sharing, thank Nelson

There's two main reasons I didn't use folded cascodes.
...
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Old 12th September 2006, 10:49 PM   #17
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Quote:
Originally posted by CheffDeGaar
A more practical one, as I needed a little more open loop gain which I guess I couldn't achieve with a mere folded cascode
There are some practical disadvantages to cascodes and
folded cascodes in particular - they don't add much loop gain,
they are more complex (than nothing), and they cut into the
voltage swing of the circuit relative to the supply.

The advantages are that they provide faster and more linear
operation for the gain devices, and they also allow the use of
better, more refined (read: delicate) devices.

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Old 13th September 2006, 04:30 AM   #18
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Default Simulation Headaches

Iím intrigued with this UGS circuit and would like to learn its workings. I usually play with PSPICE (LTSPICE) to work through the operation of a circuit, but Iím having issues with Cheffís (et al.) circuit. I know folks here have their reservations about usefulness of spice (Iím agreeing), but it has, in the past, helped me build confidence in the design both in its function and my understanding of it, especially when I can finagle the parameters to produce the desired output.

I am having problems with the simulation output. Given an input frequency/amplitude, there is a positive absolute DC offset at the output, irregularity of pos/neg outputs around center, and glitches/spikes. I believe my problem lies in the JFET models and/or my application of them. Have any others simulated this circuit successfully? Any recommendations for taming the offset Iím seeing? Yeah, I know I could just build it, but those JFETs arenít too cheap or easy to come by. Also, have any tried building this with matched 2sj109/2sj74 JFETs?

Thanks, Willus
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File Type: pdf ugs_pre_1.pdf (10.1 KB, 1387 views)
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Old 13th September 2006, 04:30 AM   #19
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Default Simulation Headaches

And the Waveform Output.
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File Type: pdf ugs_pre_sim_1.pdf (33.2 KB, 812 views)
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Old 13th September 2006, 07:27 AM   #20
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Willus,

I haven't had problems with spice for this circuit, and I really don't know where your irregular offset comes form...
Here are the JFets models I've used for testing :

.MODEL 2SK389BL NJF (VTO=-420.565M BETA=62.7612M LAMBDA=1M IS=10F RS=8.03465
+ CGD=19.8997P CGS=24P KF=0.00222996F AF=500.504M)

.MODEL 2SJ109BL PJF (VTO=-418.894M BETA=83.8035M LAMBDA=1M IS=10F RS=11.0887
+ CGD=71.6975P CGS=61.6464P PB=1.85382 KF=0.00787907F AF=499.474M)

Sure, the circuit can be built using matched 2SK170 and 2SJ74, but you'll have to match them both in Vgs and transconductance (different Vgs at different drain currents), and make sure their thermal coupling is efficient.

Zetex BJTs are nor mandatory here IMHO, and any low power BJT with gain > 100-200 will do.

Regards
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