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Old 9th January 2006, 09:05 AM   #1
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Default F1 and questions

When I built F1, I prepared 2 x 5 holes (of 4mm dia) on the heat sink per channel for installation of IOR IRFP250Ns. I first built F1 with 5 Mosfets per channel as original. Later, I added 5 more Mosfets per channel, which I kept as spare, in parallel with the already installed 5. The paralleling was by simply soldering G to G, D to D, and S to S. See the attached picture for reference. (I kept my total bias of 1.2A and the Aleph ac current gain of about 25%.)

By paralleling in this way, I might secure longer Mosfet life. In addition, I guess that, as each Mosfet shares half bias, the transconductance of each Mosfet would be reduced (i.e. ac resistance increased) at certain degrees. Therefore, the Av (voltage gain) would be reduced. It means that Miller’s input capacitance might be reduced.

Are there any other pros and cons in this way of paralleling? Thanks for all kind of advices.

Regards
jh
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Old 9th January 2006, 09:19 AM   #2
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One con is the input capacitance
is doubled at the Gates.

If your driver stage delivers large amount of current
this may work well anyway in your setup.
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Old 9th January 2006, 12:58 PM   #3
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Thanks, lineup.

Well understood that the input capacitance is simply doubled up due to the paralleing them. Behind them, no magic.

Any other cons (or any pros)?

Regards
jh
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Old 9th January 2006, 04:22 PM   #4
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Hi jh6you,

Just connecting the mosfets in straight parallel is probably not a good idea because of potential current hogging. It won't blow up, but you won't get the benefit you're looking for. Each transistor should have its own source resistor.

Regards,
Graeme
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Old 9th January 2006, 07:15 PM   #5
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I just looked at your photo again. If your paralleled mosfets are mounted side by side on the same size heat sink as the single transistors were then your final heat sink temperature will be the same for the paralleled version. P = V x I where P is heat. You are just trading I = 1.2 for I = 2 x .6.

Reducing the current from 1.2A to .6A will not seriously extend the life of a big mosfet like a 250. Reducing the heat might - depending on the temperature they are operating at now and the reduction in temperature you achieve.

Graeme
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Old 10th January 2006, 12:19 PM   #6
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Hi Graeme

The "potential current hogging" makes me feel fear. I will arrange the separate source resistors as it's not a difficult job.

By the way, I remember that power MOSFETs have negative temperature coefficients so that direct paralleling of them without external components are ok as there will be no thermal runaway (current hogging). I might have understood merely part about it . . . ?

With the double Mosfets, my heat sink temperature rise average 20 degC. I think this value is the same as with the single Mosfets (acc. to P=IV). This tells me that, if there is no change in thermal resistance, I would have half case temperature per Mosfet when they are paralleled. Is it right . . . ?

Tks.

Regards
jh
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Old 10th January 2006, 12:50 PM   #7
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Quote:
Originally posted by jh6you


With the double Mosfets, my heat sink temperature rise average 20 degC. I think this value is the same as with the single Mosfets (acc. to P=IV). This tells me that, if there is no change in thermal resistance, I would have half case temperature per Mosfet when they are paralleled. Is it right . . . ?

Tks.

Regards
jh

not case temperature,at least not significantly,just because it must be something above heatsink temp.

die (dye?,chip,whatever) temperature per each mosfet will be almost halved
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Old 10th January 2006, 03:54 PM   #8
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Hi jh6you and choky,

Yes, at half the amperage the die temperature of a given mosfet will be reduced and so will the thermal gradient between the die and the heat sink for the double transistor version, However, the same amount of heat energy (calories) will still enter the heat sink for single vs. double mosfets.

The Nelson Pass papers on matching transistors contain good discussions on the affect of mismatch vs. current splitting between paralleled mosfets.

In order to get to the negative tempco point of vertical mosfets the current needs to be much higher then what you're using.

As I see it you have three choices if you want to reduce the temperature of your mosfets: 1) reduce your bias current (bad idea sonically), 2) increase the size of your heatsinks (expensive idea), or 3) add a fan (noisy idea). I vote for bigger heatsinks.

I hope this helps.

Regards,
Graeme
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Old 11th January 2006, 02:54 AM   #9
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With your double die setup, wouldn't the current capability be much higher? With that setup i'd be inclined to think that your itchin to raise bias, and the rails....I would, but thats me.
A few 24v fans run at 12v might do the trick, if a bigger heatsink is out of the question. F1 max output current is 1.75, I wonder what 5 or 10 amps would sound like? If you go that route i'd be interested what the results you had with orig F1 vs. your modified setup.

John
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Old 11th January 2006, 06:55 AM   #10
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Graeme

Sure, was much helpfullll.

By the way, I gave up the paralleling.
I cut the lines, but the spare mosfets still stay on the heat sink.
If I remove them from the sink, I will get back 5 empty holes. You know . . . ? That is no good . . . all empty holes I see always encourage me to fill them up with something. I don¡¯t know why . . . I let the spare mosfets stay there and hide the holes.

Later, having good time, I will use the holes for measurement of mosfets on a real life condition.

Tks.

Regards
jh
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