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Old 22nd December 2005, 05:48 AM   #1
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Question BOSOZ input DC offset tolerance

What is the upper limit for DC offset at the inputs of the BOSOZ... and what happens when the offset is above that value?

(Balanced inputs, same offset on both + and - inputs, circuit as described in Mr. Pass' article.)

I tried modeling it in PSPICE, but am not sure what to look for as I increase the input DC offset.

Thanks for your help!
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Old 22nd December 2005, 07:58 AM   #2
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BOSOZ amplifies any error voltage occurring between +/- inputs. Even if the error voltage is a dc, it would be amplified. But it would be no technical problem because BOSOZ has the dc blocking output caps. Anyhow, I would avoid error dc voltages greater than 200mV (by rule of thump, assuming 20dB gain).
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Old 24th December 2005, 05:43 AM   #3
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Thanks for the rule of thumb!

I'm not sure I understand what the effect is when there is excessive offset and why it needs to be so low. In the simulation, I could see the voltages changing and more current flowing through the FETs as I changed the offset. When I set the offset at +3 volts for both the + and - inputs, I expected to see some clipping in the output waveform. I didn't see it, but I'm afraid I just don't know what kind of distortion to look for...

Should I see some clipping or does the negative result of excessive DC offset exhibit itself in some other way in this circuit?
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Old 24th December 2005, 07:57 AM   #4
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Quote:
Originally posted by Henry Pootel

When I set the offset at +3 volts for both the + and - inputs, ...

Then, the error voltage is zero to the inputs.
Nothing will appear at output (on the assumption that the gain values on +/- sides are equal).

Happy X-mas !!!
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Old 29th December 2005, 11:04 PM   #5
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Yes -- from a common mode perspective -- if the offset is equal on both + and - inputs, then it shouldn't affect the output.

However, there is more going on in the circuit, isn't there?

The input goes into the protection diodes and the base of an insulated gate transistor. So, I suppose that these will place an upper limit on DC offset, but that limits it to... what.. around 5 volts? Above that, we'd see clipping and/or distortion, I think... but that's a pretty large offset.

The reason I am thinking about this is that I have a DAC chip that has a +2.6 volt offset for both + and - and want to connect it to the BOSOZ input. So, the choice I am pondering is: which is worst, a coupling capacitor or DC offset.

I was thinking that the effect of this 2.6 volt offset would be poor distortion performance. Looking at figure 10 in Mr. Pass's paper, I was wondering what the curve would look like for a 60v rail, but a DC offset of 2.6 volts. (Oh, for some test equipment so I could measure it myself!) Would it look like the 50v volt rail distortion curve because of the higher gate voltage?

If you were choosing between a coupling capacitor and a 2.6 volt DC offset, which would you choose?
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Old 29th December 2005, 11:53 PM   #6
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I would choose the coupling cap.
I have BOSOZ too. Before I had no input coupling cap while now have 1uF film cap of cheap price. I hardly detect difference in sound.

Regards
jh
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