Hi All,
Throughout the Zen articles by Nelson Pass, he kept suggesting that his designs were building blocks to be combined and matched together.To this end, I had the idea to insert power JFETS into the AlephX output stage. The image attached is a first stab, based on Nelson's cascoded JFET amp and the AlephX design. Please note I have not yet simulated this, although that won't be too far off. I'm sure the schematic has errors also...
I thought 'd run it by ther forum to see if this is a feasible and sensible enhancement to the AlephX.
The main issue is the JFET requires a -ve voltage on its gate, hence the 4.5V 'batteries' to produce the DC voltage shift. In the real world, these could indeed be real batteries (bypassed by signal caps). They won't need to produce any current, save the gate capacitance of the JFET. I fully expect this to cause havoc with the already troublesome DC output issues of the AlephX.
Any comments or suggestions...
By the way, where can I get a PSPICE model of the power JFETS Nelson is using??
Throughout the Zen articles by Nelson Pass, he kept suggesting that his designs were building blocks to be combined and matched together.To this end, I had the idea to insert power JFETS into the AlephX output stage. The image attached is a first stab, based on Nelson's cascoded JFET amp and the AlephX design. Please note I have not yet simulated this, although that won't be too far off. I'm sure the schematic has errors also...
I thought 'd run it by ther forum to see if this is a feasible and sensible enhancement to the AlephX.
The main issue is the JFET requires a -ve voltage on its gate, hence the 4.5V 'batteries' to produce the DC voltage shift. In the real world, these could indeed be real batteries (bypassed by signal caps). They won't need to produce any current, save the gate capacitance of the JFET. I fully expect this to cause havoc with the already troublesome DC output issues of the AlephX.
Any comments or suggestions...
By the way, where can I get a PSPICE model of the power JFETS Nelson is using??
Attachments
Hi,
The whole idea of Nelsons article was he was running them with a gate voltage around 1 volt below the souce pin, hence giving it the 'Triode' like behaviour. It also allowed Nelson to use the lovely self biasing feature of a -ve gate voltage.
Unfortunetly, In the AlephX, unless we want to throw away a lot of voltage and power by having a large source resistor below the JFET, we must use some other way of producing the DC shift of the signal.
Perhaps someone else can see something I can't
Adrian
The whole idea of Nelsons article was he was running them with a gate voltage around 1 volt below the souce pin, hence giving it the 'Triode' like behaviour. It also allowed Nelson to use the lovely self biasing feature of a -ve gate voltage.
Unfortunetly, In the AlephX, unless we want to throw away a lot of voltage and power by having a large source resistor below the JFET, we must use some other way of producing the DC shift of the signal.
Perhaps someone else can see something I can't
Adrian
As a practical matter, you have to throw away the voltage.
In this case, you lose about a volt on the Source resistor,
about2 to 3 volts on the JFET and about 2 volts on the
Mosfet, so figure on a 6 volt loss instead of the usual 2.5
or so. You can either ignore it, or you can make the negative
supply higher voltage.
In this case, you lose about a volt on the Source resistor,
about2 to 3 volts on the JFET and about 2 volts on the
Mosfet, so figure on a 6 volt loss instead of the usual 2.5
or so. You can either ignore it, or you can make the negative
supply higher voltage.
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