DC offset problem Aleph 5

[Adrie]

I've built one Aleph5 channel and it's working great

I built the 2nd channel and there's a offset problem
I check all values so far carefully.

All major DC values seem to be OK
Bias current is 0.62A per FET

After switching on the supply the output is rising to -5 to 6 V and the DC value is demping out in about 15 sec to values under 200mV. It is even coming down to 50mV what it should be
Switching off the supply makes the output rising to 5-6V and it demping to about 2 V in 10 sec or so and then it takes much longer. There is a speaker connected, a mid range with a capacitor in series. Without speaker same behavior.

Sounds seems to be fine so far although the connected midrange is an golden oldie.

When connecting a 22 power R over the outut the DC offeset is demping out a bit faster.

This behavior is also there with pur resistive load of 22R and without any load

No oscillations to see on the scope.
Has anyone see this before ?
Any advice ?

[janneman]

Adrie,

I'm not sure there is a problem. The transient offset is generally seen with SE amps - I think yours is SE? The 55mV is OK.

If you connect both channels, with same load, to same supply, at the same time, do they act differently? How long is the transient offset with a resistive load (no cap in series) of say 8 ohms?

Jan Didden

[Adrie]

Thanks Jan for your reply,

Yes my amp is SE.
The reason why I got suspicious is that the test midrange died last week.

The transient takes up to 10 sec or longer to under 1-2V and that's long

I just tested the other channel and it showed now similar behavior.

With resistive load only 22R, no power on transient and a minor power off transient of les than 2 sec, so thats ok

Regards,

Adrie

[janneman]

So there you have it: no problem, but make sure that there is a resistive load to limit the transient. Or go to push-pull ...

Jan Didden

[wuffwaff]

Hi,

I think this is usual. My A5 also goes to 3.6V (with 4Ohm speaker) and then back to (almost) zero. There must be apost somewhere discussing this behaviour.

William

[Blues]

Adrie,

Have you tried NP's solution on the A30/60 (R8*) for DC offset? A resistor (start at 100k going down) from gate of Q2 to CCS Drain (Q3) and Q1/Q2 Source node.

[Adrie]

It wasn't needed at the end.

Thanks all for your suggestions