The Aleph-X

[HarryHaller]

I find myself in complete agreement with Mr. Rollins. I plan to go build the thing and fine tune any issues like bandwidth or DC offset later. I may play with a servo later but find the 30 ohm resistor solution both reasonable and practicle, even for a commercial version. Analysis is paralysis. As Mark Twain said "Everyone talks about the weather but no one does anything about it." DC offset is diffcult to simulate be cause of thermal effects but very easy to measure, when a few of the Aleph Xs are bulit we can pool our experiences to address any concerns about offset. Back to the workbench.....

H.H.

[Peter Daniel]

I'm in agreement with the above as well.

[tvi]

My work in progress, please point out errors, and criticism is welcome.

Single sided, with just two jumpers and a bit of lead bending for Q5 & Q7.
R1, 2, 3, 4, 18, 19 28, 29, 42,43,44,45 are not on the board

Getting R19, 29 of the board helped alot, I would put them on the input connectors with R18, 28.

I used Proteuslite from <a href="http://www.labcenter.co.uk/">labcenter.co.uk</a> the bitmap is not to scale.

Regards
James

[Peter Daniel]

It would be better if input differencial could share the same heat sink for temperature stability. You used jumpers to get connections for R9 and R38. Wouldn't it be better to put them on opposite sides and avoid jumpers?

[tvi]

Amazing how different things look after a good nights sleep, I will new post a PCB/Schematic after 4AM (Aust time) again.

The pads are a bit small, the 3w resistors aren't sized for 3W Metal Oxides, but the layout looks much better and is hopefully more accurate.

No jumpers and R18/28 are on the PCB.

Is mounting Q5/7 front to back a good idea, no one makes the same device with a mirrored pinouts that I know of.

Can post the Proteus layout file if anyone wants it?

Any comments??

James

[Peter Daniel]

I don't see that differencial pair can use the same heatsink. It looks that the biggest complication in your layout are the traces from input differencial to the gates of output devices. You run them crossing ea. other. You have to run the trace between the legs of input mosfet and it means that the legs have to be bent quite a lot for different spacing. In my book it's no good. Mosfet should go into the board without need for leg "streching". Don't cross those traces, but run them in opposite directions. It doesn't change much because you connect wires to PCB anyway but the layout becomes better.
I just finished Aleph5 and put all 3 input mosfets on one heatsink. When I checked, it is pretty warm.

[sonnya]

Hi Grey!

Just a short question what is the idle current in the current source for the diff pair?

What is the idlecurrent in the outputstage?

I am going to simulate this weekend (Maybe friday?).

I have trouble finding the model for the IRF9610. Do you have any ? Harry?

If i am not finding one i will try see if i can find another device close to the IRF9610 for the sim.... Not good!!

I have a small suggestion.. reduce the of the feedback resistor by 3 times (10k and 100k => 3k3 and 33k) and at the same time raise C2 and C4 3 - 5 times (33p - 47pF).

This should also have a influence (improve) on the phase margin ... But first i will do a sim with the original circuit.
When i have done this i will upload some curves on the freq. response.

Sonny

[GRollins]

Sonny,
--The bias for the front end is about 20mA total, or about 10mA per side.
--Output stage bias is on the order of 2.27A for the circuit as published, i.e. with output bias set for .5V across the Source resistors.
--IRF models? None here. Sorry, I lost all my simulation stuff when the virus hit. I didn't even try to save that; the stories were more important. All I can do is suggest www.irf.com to see if they have it available for download. For accuracy's sake, keep in mind that I'm using IRF MOSFETs and OnSemi MPSA18s here, not Zetex '450s or any of the other likely candidates. Substitution may or may not give useful results...but on the other hand, someone is guaranteed to want to use the Zetex parts with Toshiba MOSFETs (or something...), so I'm sure that any simulation will be of interest to someone, somewhere. Just be sure to specify what models you use.
--Reducing the feedback will increase the measured distortion and reduce damping factor. Whether it will sound better or not I will leave to others. Bear in mind that the closed-loop gain will increase somewhat. This may or may not be a good thing, depending on your circumstances.

I'm still working on a PCB layout. (Have yet to look at the one posted above.) I've started a new pattern that may (if I'm lucky) allow me to post a single-sided board diagram. Maybe. It's slow going and further complicated by having a relative in poor health; my attention is divided at the moment. I'll keep plugging.
I still haven't built even one proper channel. Aside from the medical situation mentioned above, I need to commit to some sort of heatsink. Part of me says to go water-cooled (just build what I need), the other part says to go passive air cooled (in which case I'm at the mercy of what's available on the surplus market--you know that story).
As Pooh says,"Oh, <i>bother!</i>"

Grey

[grataku]

I just finished my layout it's a board with everything on it, it has a single layer and symmetrical (for the most part). However, I don't think it is quite mature for public scrutiny, yet. It will be awhile, quite frankly my motivation is terrible, it's the summer, it's hot and I am thinking more on the line of 'Corona with lime' rather than class A amps.
I am also trying to do a board with 3 mini-A on it which is going to be painful.
Grey,
sorry about your family problems. I hope everything is resolved for the best.

[HarryHaller]

.SUBCKT IRF9610 10 20 40
* TERMINALS: D G S
M1 1 2 3 3 DMOS L=1U W=1U
RD 10 1 1.42
RS 30 3 76M
RG 20 2 83.3
CGS 2 3 155P
EGD 12 0 1 2 1
VFB 14 0 0
FFB 1 2 VFB 1
CGD 13 14 193P
R1 13 0 1
D1 12 13 DLIM
DDG 15 14 DCGD
R2 12 15 1
D2 15 0 DLIM
DSD 10 3 DSUB
LS 30 40 7.5N
.MODEL DMOS PMOS (LEVEL=3 VMAX=417K THETA=58.1M ETA=2M VTO=-3.1 KP=0.865)
.MODEL DCGD D (CJO=193P VJ=0.6 M=0.68)
.MODEL DSUB D (IS=7.47N N=1.5 RS=2.81 BV=200 CJO=151P VJ=0.8 M=0.42 TT=240N)
.MODEL DLIM D (IS=100U)
.ENDS