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Old 22nd June 2004, 11:46 PM   #1
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Default GC SuperSymmetry part IV

Then there are those who only want Chips in their amp.

www.passlabs.com/np/GC-SS-4a.pdf

In this case the output stage consists of both series and parallel
chip amps. The voltage sources you see introduce differential
DC offset between the two parallel chip amps, which allows
a DC bias current for the amps which can be set arbitrarily.
This DC bias is not seen by the load which sits beween the
output resistors. The damping factor remains high, as it is
enclosed by the GC input pair.

I leave it to you to decide what constitutes an acceptable
bias current for the chip amps.

Like the other versions, note the chip amps each having their
own local (nested if you like) feedback loops. Adjusting these
loops will give a wide range of performance/stability character.

As with version 3, we can easily arrange to invert the input
pin polarities of the chip amps, but that would be a trivial
variation after the first example.

There will be a prize for the first person to find a mistake
in any of the four.

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Old 23rd June 2004, 12:55 AM   #2
gl is offline gl  United States
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Nelson,

In the first version there is a missing value for R3.

Graeme
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Old 23rd June 2004, 04:39 AM   #3
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This being a symmetric circuit, I invite you to look at the
part on the mirror half.
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Old 23rd June 2004, 06:59 AM   #4
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Confused:

The input stage chips of 4a should have -/+, not +/-. I'm really confused.
And... and I clearly see the complexity inside Nelson's brain while he speaks out so simple.
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Old 23rd June 2004, 11:02 AM   #5
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Pepper:

I see that the four output stage chips of 4a are utilized only with their half capacity at maximum. If so, 2a or 3a are more intersting potential projects?

And... and if it is full of emptiness inside his brain, he would speak out very much and long.
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Old 23rd June 2004, 01:23 PM   #6
moamps is offline moamps  Croatia
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Hi,
paralleled chipamps haven't same AC input signal (or always same tracking difference) what means that one is dynamically loaded with very low impedance from another. This design doesn't look good to me, but maybe I'm wrong.
Regards
Milan
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Old 23rd June 2004, 06:33 PM   #7
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Quote:
Originally posted by jh6you
Confused: The input stage chips of 4a should have -/+, not +/-. I'm really confused. And... and I clearly see the complexity inside Nelson's brain while he speaks out so simple.
No, I believe that's correct. We just keep flipping the polarities
until it comes out.
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Old 24th June 2004, 08:09 AM   #8
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Red.hot.chilly.pepper:

The 4 inside should have the flipped polarities. Otherwise, I give up this project...??? Because of .........................
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Old 24th June 2004, 08:46 AM   #9
uli is offline uli  Austria
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Default inverting topology

Quote:
Originally posted by jh6you
Red.hot.chilly.pepper:

The 4 inside should have the flipped polarities. Otherwise, I give up this project...??? Because of .........................


You need not give up.

As the 2nd OPA gets its inputsignal from the supply shunt resistor

of the first one the phase is 180.

Imagine driving OPA1 with positive signal -> output gets positive

thus drawing current from PSU -> this in turn leads to more

voltage across that shunt -> this again leads to negative voltage

at the capacitor coupled input of the 2nd OPA -> Bingo!


Uli

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Old 24th June 2004, 09:42 AM   #10
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Mist.on.my.shoulders:

I well arrive to your Bingo position. Thanks.
After all of that, where to where the supply currents of the second OPAs flow? From this point, my face starts to have harmonic distortion.
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