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Old 22nd July 2013, 05:34 PM   #821
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Got objective data which shed light on the inner workings of the schematic in the above post; which is also reproduced here. Here are key details of the test:
  • Balanced input signals to the diff amp were offered via the secondary windings of a toroid step-down [120V to 12v] transformer.
  • Sine test signal at 130 Hz.
  • AC multimeter measured voltages at the selected nodes in the circuit of the attached schematic.
  • Note switches Sl and Sr at the power output of the amp. When open [Case 1], the resulting balanced amp operated in the open loop mode [no SuSy]. By contrast, SuSy was enabled when the switches were closed [Case 2].
The data are in the second picture. One calculates in Case 1 [open loop]:
  • The voltage gain of the diff amp is ~10
  • The open loop voltage gain is ~240
  • Note the close matching of the two channels in S/150; a needed property to enable perfect SuSy
Case 2 [closed loop] gave the following results:
  • The voltage gain of the diff amp is ~1.3
  • Closed loop gain of the banlanced-SuSy amp is ~33
  • Voltage gain invested in negative feedback = 17 dB; to mostly correct for error in diff amp; because the performance of S/150 is pristine by design.
To attain the full power output capability of the resulting balanced-SuSy amp, the constant current source feeding the diff amp must be beefed upward of 100 mA or more. The voltage swing in the load resistors of the diff amp is the input signal to S/150; calculated to be >3 Vp-p to give 70 Vp-p output voltage for each channel of S/150. The current swing in each load resistor of diff amp is >30 mAp-p. metalman found this requirement in a past post.
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Old 23rd July 2013, 09:29 AM   #822
vtr is offline vtr  Switzerland
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Question to the ssgc builderīs

is the schematic in post 439 still the last one?

and anyone tried with fet input stage (there have been some comments that bipolar is better there but i donīt know why)

thanks
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Old 23rd July 2013, 04:04 PM   #823
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Quote:
Originally Posted by vtr View Post
Question to the ssgc builderīs

is the schematic in post 439 still the last one?

and anyone tried with fet input stage (there have been some comments that bipolar is better there but i donīt know why)

thanks
The thread had gone stale for 2+ years. It is possible that the builders of ssgc had already unsubscribed. Maybe a PM to metalman [owns post 439] will help.
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Old 23rd July 2013, 05:19 PM   #824
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We made boards for this a long time ago, but have since moved on. They used the ZTX bipolar front end.
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Old 23rd July 2013, 06:42 PM   #825
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Quote:
Originally Posted by BrianDonegan View Post
We made boards for this a long time ago, but have since moved on. They used the ZTX bipolar front end.
Thank you for the info.
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