Zen V4 phase
 

From a simulation carried out with Spice that turns out me Zen V4 inverts the phase between input and output.
Some one knows if this is corrected?

:D :D :D
Yes - it is written in the Zen V4 article!!! Input is +, output is -. You ran it through spice to find that out :):):)!!!

Referring to http://www.passdiy.com/pdf/zenamp.pdf, Fig.2, I would presume it as follows:

If a +v(ac) signal is applied to the input, it would increase Vgs of Q1, and accordingly an increased current greater than the bias current would flow through Q1. Meanwhile, only the constant current is allowed to flow through Q2 (CCS). Therefore, the net increased current should flow to the output coupling capacitor. Then, the voltage across the output capacitor would be reduced—i.e. (1) by as much as –V(ac).

At the same time, the +v(ac) input would reduce the current flowing through R8. Then, the drain voltage of Q1 would be reduced—i.e. (2) by as much as –V(ac).

The above two actions happens at the same time in order to be (1) = (2).

I hope my presumption is not bad.

Truly I was experiencing a new one input baffer and it is then that I have noticed the thing, otherwise I would not be shrewed. However thanks.