F5 dc offset issue

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> JFET gates are just junctions like any transistor or chip. There is a historically popular "36V process", which is why so many opamp chips are rated +/-18V MAX. 99 out of 100 will survive 40V for years, though maybe not decades; and of course that uncertainty is why we are told "36V".

May I ask if you do know, or if this is your speculation ?
Have you perhaps measured the actual breaksown voltage of the GS or GD junction of a 2SJ74 ?
Or can you perhaps explain the different Vgds specifications of 2SJ74 (25V), 2SK170V (40V), 2SK246/2SJ103 (50V), if they are all from the "historically popular 36V process" ?

Just for interest, there are also JFETs with much lower Vgds, such as the beloved BF862 (20V).
2SK932, 2SK3557 are even lower at 15V, even though the latter is almost identical to BF862 in spec.
Many of the datasheets will have a graph of gate current against voltage.
One can easily see at what voltage they begin to increase significantly.

Vgds (the gate-drain breakdown voltage) is specified at that when the gate current goes beyond µA level.
Some manufacturers specify that at 1µA (J111), some at 10µA (2SK3557), some at 100µA (most Toshiba's).
And normal gate current is ~100pA level.


Cheers,
Patrick
So if I were to leave my F5Tv2 without a cascode, is that acceptable?
 
The Toshiba datasheet says :

Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings.

So it depends on how much reliability risk you want to take.
If you would only use a 150W rated IRFP240 at only 25~30W,
I do not see the logic of running the JFETs beyond their maximum rated voltage.


Patrick
 
The Toshiba datasheet says :

Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings.

So it depends on how much reliability risk you want to take.
If you would only use a 150W rated IRFP240 at only 25~30W,
I do not see the logic of running the JFETs beyond their maximum rated voltage.


Patrick
Agree. I guess I have only one choice of running it till it fails now.
 
I would suggest testing a new unused JFET for gate current at the operating point of your circuit. Then unsolder the suspect compenent and test that. If you don't have spares, you should acquire some.

I did this recently in a soldered proto board and the transistor was not the problem.

If you do not know what the problem is for certain, you should spend your time and energy becoming certain of what is the problem.
 
Thanks for the help guys. Luckily, I do have more jfets to test.

First I might try a small cap across feedback resistors as outlined in the f5t article to combat oscillation. If there is no change I will move on to replacing jfets.

On the other hand, I’ve been studying Alephs for a while and maybe now is an opportunity to make a change.

Aleph 5 in diyaudio 5U chassis might be too much heat though. And my speakers are a big 3 way with a 3ohm min (nominal 8 ohms) so it might not be the best choice. Always tinkering...
 
I have run my BA3 at 30 volts for years with no problems. Toshiba jfets.

Russellc

So had I. I’ve run a BA-3 front end at 32V for a few years. And this F5t for a year or so before I noticed something was wrong. It’s not something that is readily apparent.

Man, these toshiba jfets are hard (and expensive) to get these days. I have another set but they reside in a B1 rev2 buffer currently.
 
Swap them with the other channel if you are short on parts. At least
then you will know.

i did end up swapping the other channel's jfets to the channel that is misbehaving.

Issue still exists. 10mv DC offset with inputs open and -180mv DC with inputs shorted. So I guess it's not leaky jfets after all.

Any other ideas? Bias is stable and even across all mosfets.
 
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