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Y.A.F5Tv3.B.T. Yet another F5Tv3 Build Thread
Y.A.F5Tv3.B.T. Yet another F5Tv3 Build Thread
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Old 19th October 2017, 09:36 PM   #21
2 picoDumbs is offline 2 picoDumbs  Australia
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The jfets aren't that sensitive to Vds.
Your choice.
I would be happy at anything between 13V and 20V on the jfets.

Usually a good rule of thumb is maximum peak input signal + 10V. Assuming 2.8V peak input then 13V is quite good.
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Last edited by 2 picoDumbs; 19th October 2017 at 09:40 PM.
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Old 19th October 2017, 11:22 PM   #22
gionag is offline gionag  Italy
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Quote:
Originally Posted by 2 picoDumbs View Post
The jfets aren't that sensitive to Vds.
Your choice.
I would be happy at anything between 13V and 20V on the jfets.

Usually a good rule of thumb is maximum peak input signal + 10V. Assuming 2.8V peak input then 13V is quite good.
Good to know. for 13v is 4k
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Old 20th October 2017, 12:00 AM   #23
gionag is offline gionag  Italy
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In the calculation, i have to account the dissipation of the 8 mur3020 ?
from my point of view, they have a very low resistance, so the heat dissipated is quite low... but maybe i am wrong.
From before i have estimate a total power dissipation from the mosfets, but how i need to weight the diodes ? (from a thermal perspective)

Every channel has 8 mosfets and 8 diodes, in the attached simulation i have calculated with a total power dissipation of 140w (and an ambient temp of 30degC).
I think i can push a little bit more on this chunk of aluminium.
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Old 20th October 2017, 12:48 AM   #24
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Y.A.F5Tv3.B.T. Yet another F5Tv3 Build Thread
in moments of peak currents , current is practically subtracted from mosfets , and given to speaker

so , sum dissipation on heatsink is declining ,so you can ignore dissipation on/through diodes

if you're going full bang , counting on heavy AB class work of F5T , then you really need to carefully calculate everything .....
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Old 20th October 2017, 08:30 AM   #25
AndrewT is offline AndrewT  Scotland
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Quote:
Originally Posted by 2 picoDumbs View Post
The jfets aren't that sensitive to Vds.
Your choice.
I would be happy at anything between 13V and 20V on the jfets.

Usually a good rule of thumb is maximum peak input signal + 10V. Assuming 2.8V peak input then 13V is quite good.
the input jFET is a voltage to current conversion stage.
You input a voltage and the jFET output is a current.

The input jFET can operate with a Vds of 2 volts even though the input voltage can swing to over 2Vpk.
If you add on a cascode you can run with a Vds anywhere from ~2Vds to the maximum where base current leakage starts to become unmanagable.

The drain resistor converts the output current back into a voltage read by the next stage.

This drain resistor having a voltage output is what needs voltage to allow that swing.
The drain resistor is above the cascode.
The jFET does NOT need an extra 10V above the input signal.
The purpose of the cascode is to separate the jFET from the effects of the high supply rail voltage.
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Old 20th October 2017, 07:28 PM   #26
gionag is offline gionag  Italy
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Originally Posted by AndrewT View Post
the input jFET is a voltage to current conversion stage.
You input a voltage and the jFET output is a current.

The input jFET can operate with a Vds of 2 volts even though the input voltage can swing to over 2Vpk.
If you add on a cascode you can run with a Vds anywhere from ~2Vds to the maximum where base current leakage starts to become unmanagable.

The drain resistor converts the output current back into a voltage read by the next stage.

This drain resistor having a voltage output is what needs voltage to allow that swing.
The drain resistor is above the cascode.
The jFET does NOT need an extra 10V above the input signal.
The purpose of the cascode is to separate the jFET from the effects of the high supply rail voltage.
said that, there is a particular sweet spot for the sk170/sj74 ?
i also imagine that if the cascode device needs to regulate more and more the voltage down then its dissipation figure start to increase. not so much because the current involved are very little...
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Old 20th October 2017, 08:44 PM   #27
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Y.A.F5Tv3.B.T. Yet another F5Tv3 Build Thread
one can have different understanding , when looking at device load lines graph

in other words - I personally don't like having device starving , neither in voltage nor current

take care to have 10-12V as D-S voltage for JFet , around 90% of Idss and you're there
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Old 20th October 2017, 10:52 PM   #28
2 picoDumbs is offline 2 picoDumbs  Australia
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Quote:
Originally Posted by gionag View Post
said that, there is a particular sweet spot for the sk170/sj74 ?
i also imagine that if the cascode device needs to regulate more and more the voltage down then its dissipation figure start to increase. not so much because the current involved are very little...
Don't get confused, just copy Nelson if you don't understand.
I notice that it is usually between 12V and 14V when cascoding.
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Old 21st October 2017, 02:03 AM   #29
gionag is offline gionag  Italy
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Nelson seems to use @ 10v on the v3 schematic with 32v rail so i will go with them.

In your opinion, there's a practical way to guestimate the power dissipation that comes from each of 8 diodes (mur3020). I want to optimize a little bit the placement of the whole board assembly on the heatsink and i am thinking to shift a little bit the board to get the most "hot" components (mosfets) in the center.
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Old 22nd October 2017, 12:18 AM   #30
gionag is offline gionag  Italy
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I was looking into power supply options...
i will start with relatively low bias setting, but i plan to rise as much as possible to extend the class-A region.

Obviously the ripple will rise with it and for limiting the input bulk-capacitance i am start thinking about something like the zenV4 capacitance multiplier / regulator.

I made a sim in spice and it seems to works quite OK. i see that i will loose some voltage and the dissipation is around 25w for 6amp bias (too much... i know).

For sure i need to swap the irfp240 with something more beefier because the power dissipation at startup exceed specs.

What do you think about ?
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