Jfet matching jig

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Too much work imo for something that will be tested in the actual circuit anyway.

If I wanted to get more spot on without access to the final application (for example if we are selling matched pairs), then I would build a stripped down version of DCB1 and B1 R2 with sockets and measure the DC on the output.

For this I see more value in adding some curve point measurements
For the DCB1 and the Pass B1 where one device is working as a CCS @ 100% of Idss and the other device is the follower with a quiescent Id of 100% of Idss then selecting by Idss is sufficient and monitoring output offset does indeed achieve that selection.
 
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Mark,
didn't you show a rig somewhere for pulsed measurement to avoid heating of the device?
Yes I did what all semiconductor companies do when measuring high currents: pulse testing at low duty cycle. Then average power dissipation = Vds * Ids * duty_cycle. If duty cycle is low then average power dissipation is also low, and the Device Under Test doesn't warm up very much.

I measured one of those superman JFETs designed for ultra low Rds analog switching and found that its Idss was 1.1 amperes! In a TO-92 plastic package! Pulse repetition rate was 3 pulses/second and pulse width was 55 microseconds, so the duty cycle was 0.017%. With Vds=10V and Ids=1.1A the average power dissipation of the JFET was 1.9 milliwatts.

I used a simple resistor capacitor network to set the pulse width, followed by a bunch of CMOS logic gates in series to get sharp, snappy rise times at the end of the chain. If you've never measured the voltage gain of a CMOS logic gate (gain = slope of the Vout vs Vin curve), please do. Apply a 5V triangle wave to the input and plot both Vin and Vout on a dual trace scope. Look at the slope of Vout: that's the gain. Tis big, yes? Keep the triangle wave frequency low (< 500 Hz) so you're looking at the DC behavior of the gate, uncontaminated by propagation delay effects.

If you're the curious type, do this experiment a second time, but measure a Schmitt Trigger logic gate like the CD40106 or CD4093 or MC14584. Notice how much larger the gain is. Zowie!
 
Mark -- you need one of these:
 

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Yikes that thing costs 3X what I paid for my Tek 576. Besides it's much more fun to slap something together yourself and make it work. There's no surprise when a piece of Tektronix gear does the job beautifully. There's a huge surprise when one of my faeces-rigs actually functions.
 
Measuring Idss & Yfs

Erno's test jig is excellent in that it allows you to measure, with a single DMM :
Vtho, Idss, Vgs at 2ma & 5mA.

But very often it is sufficient / desirable to measure Idss and Yfs at Idss.
Examples are e.g. JFET follower or input diff pair.
The following is a poor men's method to do just that.

Required :
1x 3-pin DIL socket (for DUT)
1x digital multimeter
1x 100R metal film resistor
1x 9V battery
1x 10k trimmer (preferably multi-turn)
1x headphone output of PC / laptop

I use 2SK170BL as an example.
For 2SJ74 you have to reverse polarity of course.


To measure Idss
First connect JFET gate to the 10k trimmer wiper, and one of the 10k leads to the source, the third open (for now).
Can leave at any trim position.
Connect 0V to the source, and +9V to the drain via a 100R resistor.
Measure the DC voltage across the 100R resistor.
Divide by 100R, and you get Idss.


To measure Yfs at Idss
You need to be able to generate a sine wave of 0.05Vrms 100Hz.
This you can do by simply connecting the headphone output of the PC across the 10k pins of the trimmer.
Headphone Gnd should be connected to the JFET source side.
With the JFET removed, play a 100Hz WAV file :
https://1soundfx.com/sound/57149-technology-test-tone-sine-wave-100hz-60-seconds-0db-loop
and adjust the trimmer until the G-S pins of the trimmer gives 0.05Vrms, measured by the DMM.
Then plug in the DUT, and measure the AC rms voltage across the 100R resistor via a 1µF film cap (to block off any DC).
This AC voltage divided by 5 will give you Yfs (at Idss).


Patrick

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I'm seeing appreciable drift when I measure JFETs and BJTs using DC techniques. So I'm moving in the direction of low duty cycle pulse testing. And since it turns out that a good sample-and-hold costs more than a microcontroller chip with 12-bit ADC built in, I'm moving towards a uC based test fixture.

What I hope to find, is a pair of JFETs that have identical values of two parameters:

  • Vgs, measured at Ids = Ibias
  • gm = dIds/dVgs, measured at Ids = Ibias
where "Ibias" is the drain-to-source current these transistors will carry in the final application circuit.

Matched Vgs reduces offset voltage in differential pairs, and matched gm increases linearity by maintaining the same gain for positive-going and negative-going signals.

Measuring gm can be accomplished by measuring Vgs twice, first at Ibias, and then at Ibias*(1+epsilon) for known epsilon. After a bit of algebra, we have gm = deltaIds/deltaVgs.
 
:)

Shame that you did not go the hole way :
https://www.fairchildsemi.com/application-notes/AN/AN-6610.pdf

The rational of temperature control is that JFETs are very sensitive to temperature when you are looking for l<< 1% repeatability.
Even in a well insulated building in Europe, the indoor temperature can vary > 5°C over a year.
So one cannot reliably compare matching data made in e.g. Winter vs. high summer.
A temperature oven set at say 30°C would cure that.

But if one is only looking to fine match a pair of devices (e.g. as a diff pair), one can used the attached.
Just need to make sure they are thermally tie to each other (grease + heat shrink).
Again no more equipment required than a DMM and a laptop as fun gen.


Patrick

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I'm moving in the direction of low duty cycle pulse testing.

Thoughts on this idea? An Arduino can output 0-5 V on AIO1 to drive the gate of the nmos. AIO2 can measure the voltage on the top of the source resistor to determine Ids. Vgs=AIO1-AIO2. The Arduino can automatically step through various Vgs to generate a curve from which transconductance can be estimated.

For power mosfets, Vishay suggests a 80us pulse width at a low duty cycle (e.g., < 2%). https://www.vishay.com/docs/90715/an957.pdf. This would be straightforward to implement on the Arduino.

If we wanted to stabilize temperatures, we could have a thermistor on the mosfet's heatsink and the Arduino could set the "off" Vgs to some baseline Vgs that heats the heatsink enough to reach a target voltage drop across the thermistor (gotta break out my controls textbook for the PID chapter). The "on" pulses could simply deviate from this baseline.
 

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Self-heating jig for pulsed measurement by microcontroller

Here's my current thought on a jig for pulsed measurement of Idss, especially in the context of a SOT-23 package (e.g., 2SK209, MMBFJ270). The SOT-23 DUT can be clamped onto oversized pads using a spring clamp for consistent clamping pressure. An Arduino-type device can measure Vmeas with +5V used as Aref.

The board can have a 10 Ohm DPAK power resistor switched by an NMOS to pump heat into the area around the DUT, and a PTC thermistor nearby the DUT will manage the Vgs on the NMOS to reach a consistent target temp. The SOT-23 DUT should (!) be close to the board temperature due to its relatively little thermal mass.

There's a little complexity introduced by trying to keep Vds on the DUT constant, which prevents a current sense resistor to be inserted in series. That might be an unnecessary complication, given the relative stability of Idss over Vds - thoughts?


EDIT: forgot to note on the schematic that the current through the 30k and 10k resistor on the 10V shunt is about 250 uA, and should be included in the calculation of Idss
 

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If you're going to test big power MOSFETs with big QGtot, the Arduino is going to need to supply a LOT of output current. It needs to charge up the MOSFET gate to the desired analog value (example: Vgs = 3.61V) in 20 microseconds (1/4 of your 80 microsecond measurement window). You might want to install a buffer opamp between the Arduino pin and the MOSFET gate, then install a series resistor to prevent that opamp from oscillating with a gigantic capacitive load.
 
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