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Old 6th June 2018, 09:30 PM   #1611
maartentje is offline maartentje  United States
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Originally Posted by lhquam View Post
Is that a Kairos speaker in your avatar?
Click the image to open in full size.

Sorry for the late reply.. somehow my thread subscription was not turned on.
ScanSpeak 2way i build long time ago. I don't have these anymore.

Im currently working on the F4 beast pcb design. I will show some stuff in a few weeks probably. Im going to try the opto bias parallel version.

Martin
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Old 7th June 2018, 02:16 AM   #1612
lhquam is offline lhquam  United States
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Originally Posted by maartentje View Post
...
Im currently working on the F4 beast pcb design. I will show some stuff in a few weeks probably. Im going to try the opto bias parallel version.

Martin
I recently did bench tests of the opto bias parallel version and have found some issues bias adjustment procedure. That circuit has a positive temperature coefficient, meaning that the bias current increases with heatsink, optocoupler, and zener diode temperature. In my build the bias current increases about 4mA/C of heatsink temperature. That is not necessarily bad, but it does increase the time before the heqatsink temperature stabilizes, and makes it difficult to guess the initial adjustment of the bias current. I can provide more details as needed.
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Old 7th June 2018, 11:31 PM   #1613
maartentje is offline maartentje  United States
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Is there a substantial benefit in using the Cbias capacitors?
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Old 13th June 2018, 03:49 PM   #1614
lhquam is offline lhquam  United States
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Originally Posted by maartentje View Post
Is there a substantial benefit in using the Cbias capacitors?
Referring to the schematic in post #1594, there might be three options regarding Cbias (C1 and C2):
  1. Cbias as shown in post #1594, connected between top of R10 and J313 source pin. FET has only DC source degeneration. Gain is insensitive to pot adjustment.
  2. Cbias connected between top of R10 and rail (VF+). This is the same as in the BA3 Front End, shown below. FET has full source degeneration. Gain is insensitive to pot adjustment and about 15dB lower than option 1.
  3. No Cbias. FET has full source degeneration. The open-loop gain is sensitive to the pot adjustment. Poor choice.
My amplifier was originally built for option 1, but recently modified to allow easy switching between options 1 and 2. After 3 or 4 days listening to option 2, I reverted back to the original option 1 configuration, whose sound I preferred. Since 3 or 4 minutes are required to switch between the options, my listening tests were not really A/B tests where one can quickly switch.
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Old 13th June 2018, 04:45 PM   #1615
Ian Macmillan is offline Ian Macmillan
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There is also a fourth option: Cbias connected across R8 (Rs). FET has only DC source degeneration. Gain is sensitive to pot adjustment. Probably not a great choice but worth noting for completeness.
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Old 13th June 2018, 06:06 PM   #1616
lhquam is offline lhquam  United States
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Originally Posted by Ian Macmillan View Post
There is also a fourth option: Cbias connected across R8 (Rs). FET has only DC source degeneration. Gain is sensitive to pot adjustment. Probably not a great choice but worth noting for completeness.
You are correct. I actually tried that option about 1 year ago. The main problems I saw were with the RC time constant and with the series resistance of the capacitor, and variability between that resistance between the caps on the positive and negative rails. In order to get a time constant equal to option 1 requires the capacitor to be about 5 times larger.

If you were to use that fourth option, you would also probably want to have the capacitor of option 2 so that pot adjustment does not change the gain and thus the even harmonics. If the cap series resistance is not a problem, that should result in essentially the same behavior as option 1.

Last edited by lhquam; 13th June 2018 at 06:13 PM.
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