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Old 14th April 2018, 10:19 PM   #1511
lhquam is offline lhquam  United States
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Quote:
Originally Posted by Zen Mod View Post
which one you prefer?
The high feedback measurements in the left column are best, and I have been listening to this configuration for many months. Sounds great! I have not seen any stability problems due to the high feedback.
I have not listened to either of the other two versions, and it would probably require building a complete amplifier in order to do A/B comparisons between two versions at a time.
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Old 14th April 2018, 10:34 PM   #1512
Zen Mod is offline Zen Mod  Serbia
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F4 Beast Builders
your speakers are 8 or 4R?
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Old 14th April 2018, 11:39 PM   #1513
lhquam is offline lhquam  United States
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Originally Posted by Zen Mod View Post
your speakers are 8 or 4R?
My speakers have a nominal impedance of 8 Ohms. They are the Jeff Bagby designed Kairos using SB Acoustics Satori MW16P woofers and TW29R tweeters.
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Old 14th April 2018, 11:43 PM   #1514
lhquam is offline lhquam  United States
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In post #1510, I forget to mention that the resistor values for Rcsp and Rcss must be carefully adjusted to achieve the cancellation of the opposing bias current drifts and the desired bias current.
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Old 15th April 2018, 12:43 AM   #1515
lhquam is offline lhquam  United States
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I just noticed that the distortion sweeps in the upper right corner in post #1508 was the Frequency sweep rather than the the Watts sweep. Here is the corrected set of sweeps. Notice how similar the cascode feedback and FE load versions are for both 4R and 8R loads.
Attached Images
File Type: jpg ZDxx-8R-4R-sweeps-20180414.jpg (414.5 KB, 345 views)
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Old 16th April 2018, 07:46 AM   #1516
Ian Macmillan is offline Ian Macmillan
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Originally Posted by lhquam View Post
Based on both simulations and bench measurements of long signal bursts (30 secs), both the the series optocoupler and parallel optocoupler bias circuits have a significant drift in bias as the power is increased or the load resistance is reduced. Bias increases with the series circuit and decreases with the parallel circuit.
Do you know why the bias drifts with power and load resistance? Has it to do with leaving class A or is some other factor responsible? I can see that your series/parallel combination will work but it would nice to avoid the additional complexity if at all possible.
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Old 16th April 2018, 02:21 PM   #1517
lhquam is offline lhquam  United States
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The bias drift vs. load resistance is easy to explain. For a given output power the fet current range increases as the resistance is lowered. The remaining question is why the bias changes as the FET current range increases. It is apparently due to the increasing asymmetry of the FET current waveforms as the current increases. The behavior is the different for the serial and parallel opto configurations. In the series configuration, at higher current levels (more asymmetric) the time integrated current output from the servo is insufficient and thus the voltage V(drive+,drive-) increases. In the parallel configuration the opposite occurs.

The images below show:
  • circuit topology
  • series optocoupler servo and waveforms
  • parallel optocoupler servo and waveforms
  • hybrid optocoupler servo and waveforms
From left to right are:
  • servo circuit
  • 1 W waveforms vs. time
  • 1 W waveforms vs. V(Out)
  • 1W and 25W waveforms vs. time
  • 1W and 25W waveforms vs. V(Out)
From top to bottom the waveforms are:
  • FET currents
  • LED currents
  • Opto transistor currents
  • V(Drive+,Drive-) total bias voltage
Attached Images
File Type: jpg circuit-topology.asc.jpg (39.6 KB, 288 views)
File Type: jpg 20170416-ser-bias-collage.jpg (534.8 KB, 277 views)
File Type: jpg 20170416-par-bias-collage.jpg (502.8 KB, 264 views)
File Type: jpg 20170416-ser-par-bias-collage.jpg (539.6 KB, 256 views)
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Old 16th April 2018, 04:03 PM   #1518
lhquam is offline lhquam  United States
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Here is another presentation of the behavior of the 3 servo configurations. Shown is ar the FET currents (top) and V(Drive+,Drive-) total bias voltage for a 30 second duration 20Hz 25W pulse into an 8R load. From left to right are the series, parallel, and hybrid configurations. Note the vertical scales in the plots. The bias drift for the hybrid configuration is less than 3mA.
Attached Images
File Type: jpg bias-30sec-pulse-drift-ser-par-hybrid.jpg (275.2 KB, 69 views)
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Old 17th April 2018, 01:07 AM   #1519
lhquam is offline lhquam  United States
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Quote:
Originally Posted by Zen Mod View Post
which one you prefer?
The other considerations about the level of global feedback around the output stage are the damping factor and slew rate.

Since I have not listened to the lower feedback versions of the circuit I cannot offer any opinion. I know from 7 months of listening that the high global feedback version sounds excellent.
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Old 21st April 2018, 06:52 AM   #1520
schultzsch is online now schultzsch  Europe
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Quote:
Originally Posted by WalterW View Post
Very nice artwork! Real Firstwatt, Papa's style.


This is my version of the frontend, kind of UGS - Sony VFET pt2. Learning how to use Kicad finally pays off. I can configure this PCB in many ways to experiment. With or without degeneration of the small MOSFETs, EUVL trick for the JFET's or no degeneration at all. Balanced or left - right frontend.
Swiss army knife...


I will experiment with different output stages. But I think I will build this one Generg gave us first.
Did you actually build it? Instead of using many paralleled IRFP240's, using two hockey pucks will be nice to try.

Thanks to Walter who shared with me 2pcbs I managed to build 2 balanced channels that I intend to use as a preamp after a dac.
I did some thd measurements on the run and did get very impressed by the results.
My goal was not to get the lowest thd but to see if I can tune h2/h3.
Attached Images
File Type: jpg 215AA596-ECB2-49AA-A255-C883FBD48EC4.jpg (1,003.0 KB, 92 views)
File Type: jpg D215A251-58F0-4E80-A4C1-F39139D50ECC.jpg (854.7 KB, 107 views)
File Type: jpeg CBF52060-868E-4C7C-8A7F-ECC89B70D576.jpeg (149.6 KB, 106 views)
File Type: jpeg AD36B212-C6EA-4073-B83A-ECF0FDF0CB01.jpeg (149.2 KB, 68 views)
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