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Old 28th July 2008, 07:55 PM   #1681
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At low frequencies, yes. It will alter a bit at very high frequencies.
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Old 31st July 2008, 03:52 PM   #1682
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Thanks again for your reply!

OK, here are some results from my tests:

1) I have measured the open loop gain of the amplifier shown in post # 1668 with different ground resistors at the gates (R24 / R25). The jfet source resistor is now changed to 19,3R (gives 5,2mA to each jfet and 20mA through the common source devices) and each output pair is biased with 260mA.
All measurements were done with a virtual sinewave generator from my notebook with a frequency of 1kHz (relativly high output impedance of 460R) and a very exact true RMS multimeter to measure the voltages. The follower outputs were unloaded, the negative input shorted to ground.
The following examples shows the choosen ground resistors with the resulting measured overall open loop gain:
15k / 52,3dB ; 7,5k / 48,9dB ; 5k / 46,5dB ; 2,5k / 41,8dB ; 1,66k / 38,7dB
(without these resistors the gain is something about 58dB, but than the amplifier is very sensitive and it is difficult to measure)
Result: The ground resistors behave like in theory. The amount of feedback reduction is the same amount as the input is attenuated – means: an input resistor of 15k and a virtual ground to ground resistor of 5k gives a feedback reduction of 12dB.

2) The same measuring conditions as by 1) but the jfet source resistor is changed to 47R (gives 3,5mA to each jfet and 8mA through the common source devices) results in an open loop gain reduction of only 1,5dB.
I would not take this possibility to reduce the open loop gain – the 8mA bias current is very low for driving (in the final circuit) ten paralleled mosfets and also the UGS loading resistors (R60, R61) need some AC current.

3) The same measuring conditions as by 1) but the UGS output loading resistors (R60, R61) are changed from 4,7k to 2,2k results in an open loop gain reduction of 3,8dB.
This seems to be a good alternative to throw away some open loop gain. The assumption is that there is enough bias current through the shifters. A 22V peak on one UGS output will stand for a 10mA peak through these resistor. I don’t know how much AC current is needed to drive the output stage and thus how low you can go with these resistors.

4) Also I measured the output impedance with and without feedback. I got the following results:
Input and virtual gnd to gnd resistors = 15k ; UGS output loading resistor = 2,2k (same conditions as by 3) ) gives an open loop gain of 48,5dB and an output impedance of about 1,7R to 2R.
With added feedback resistors of 332k I get an closed loop gain of 26,5dB and an output impedance of about 150mR. This reflects the amount of feedback which is 22dB in this case and thus an output impedance reduction by a factor of 12 or 13.


In the final amp I want to parallel ten follower pairs, each biased with 260mA + SE bias of 250mA. The output inpedance without feedback is than a tenth of the measured above namely something about 185mR.
Also I want to get a closed loop damping factor of 200 @ 8Ohm, which is an output impedance of 40mR. Therefore the applied feedback has to be 13 or 14dB to get that value.
With the resistor values from 4) there is 8 or 9dB to much feedback.
So the virtual gnd to gnd resistors would have to be about 2k, or the UGS output loading resistors would have to scale down.


Is it possible that the single ended input impedance is about 25k with input resistors of 15k + virtual ground to ground resistors of 15k and about 16k when changing the virtual gnd to gnd resistors to 2,5k (measured without feedback)?
Also I am a bit unsure if it is a problem to get 0,5V on the ugs outputs when trimming the diff. and abs. offset of the follower outputs to zero? This happens because of winding tolerance of the two secondaries. Each difference between positiv and negative rail voltage is given with the divider network of the bias circuit to the output. What can I do, or is the high ugs offset irrelevant?

Regards
Dirk
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Old 4th August 2008, 12:40 PM   #1683
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Quote:
Originally posted by noisefree
Is it possible that the single ended input impedance is about 25k with input resistors of 15k + virtual ground to ground resistors of 15k and about 16k when changing the virtual gnd to gnd resistors to 2,5k (measured without feedback)?
Also I am a bit unsure if it is a problem to get 0,5V on the ugs outputs when trimming the diff. and abs. offset of the follower outputs to zero? This happens because of winding tolerance of the two secondaries. Each difference between positiv and negative rail voltage is given with the divider network of the bias circuit to the output. What can I do, or is the high ugs offset irrelevant?
Why are you interested in the SE input impedance without feedback? I would assume, but don't know for sure, that the value will be approx the sum of the two resistors you mention since a diff pair has a high intrinsic input impedance. So approx 30k for two 15k resistors, but possibly a bit less in practice. I suspect your 16k value for smaller ground resistors is about right too. Once feedback is applied the value will tend to the input resistor irrespective of the ground resistor although this will increase with less feedback.

I don't really see a problem with the 0.5V offset on the UGS output since you cannot swing rail to rail with a common power supply anyway. Also you want to reserve 5V or so to avoid nonlinearities in the output stage (as Nelson mention previously) so another 0.5V is hardly going to make much difference.

BTW, thanks for the informative post about the values measured in practice - very helpful!

Ian.
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Old 4th August 2008, 10:40 PM   #1684
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Hi hi...
Thanks for your reply Ian...!

Ok first to the high ugs output offset:
That could not be right – a voltage up to 1,2V with really good matched devices? Have decided to analyse the problem....
I noticed that it is not a winding problem of the transformer, because with a symmetrical load and without a circuit both voltages were equal. Everytime when I tried to rise the follower outputs exactly to zero, the ugs outputs reached such relatively high offsets and the rails started to get unsymmetric. But trimming the ugs outputs to 0V did not show this phenomenon – only disadvantage: output abs. offset was about -70mV.
Now all seems to be logical: it is the gate source voltage difference between n and p devices caused by the lesser conduction of the p-devices (the SE-bias resistors “steals” them 25mA) and perhaps a small Vgs difference between n and p. This means that you cannot try to get both (ugs out and follower out) to 0V with an divider across the voltage bias circuit. FE and output stage have to work independently without a dc current way.
I know that it was my statement to use such resistors across the caps, but I have to revoke it - it is nonsense. There should be no need for trimming the follower output abs. and diff. offset.
The independent output stage stay very constant at about -70mV or so and this can be compensated with paralleled resistors across the 10k supply resistors. Now it really looks like a F4 bias circuit with the difference that it is driven by a voltage gain stage instead of a follower stage and the absence of bootstrapping. Also the F4 do not use a thermistor to compensate the Vgs drift.
But the published gain measuring results in my last post should be right, the removed divider was not seen by ac currents.

To the input impedance:
I meassured that just for interest. I only know the op amp standard circuits where normally no resistor is connected between virtual gnd and gnd and so it confuses me.
Also I am wondering about the specified impedance of 11k unbal. and 22k bal. in the XA60 manual. This amp is using directly on the inputs a 221k “deloading” resistor for the coupling caps, a 10k input, a 10k virtual gnd to gnd and a 221k feedback resistors for the input circuitry around the jfet. Same thing in the X5: Specified input impedance is 22k balanced – used resistors are 10k input, 22k virtual gnd to gnd and 392 feedback. I can not comprehend this ??????

At least four new measured values for the published schematic:

1) Rsource: 19,3R ; RdeloadC: 332k ; Rinput: 15k ; Rgnd: 15k ; Rugsload: 2,2k ; no feedback
measured: Vu = 48dB ; Rin = 26,8k

2) same as 1) but now with feedback: Rfeedback: 332k
measured: Vu = 26,3dB ; Rin = 19,2k

3) same as 1) but now Rgnd: 2k
measured: Vu = 35,8dB ; Rin = 16,2k

4) same as 3) but now with feedback: Rfeedback: 332k
measured: Vu = 24,3dB ; Rin = 15,4k


Regards
Dirk
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Old 5th August 2008, 05:23 PM   #1685
gl is offline gl  United States
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Dirk,

The XA60 has input impedances of 11K/22K as you say. But the XA60.5 has input impedances of 15K/30K. It is the XA60.5 circuit that you want to reference I believe. The older XA60 is the factory "Aleph-X".

Graeme
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Old 5th August 2008, 06:20 PM   #1686
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Hi Graeme,

no I don't reference to a XA60.5. The resistor network describtion is for a XA60 (Aleph-X). It uses a 2sj109 as input device driven by a current source and the mentioned resistors around. I don't understand the specified impedances in the manuals in both amps (in a balanced complementary (ugs module) and a balanced single ended configuration).

Regards
Dirk
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Old 5th August 2008, 07:11 PM   #1687
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Quote:
Originally posted by noisefree
Now all seems to be logical: it is the gate source voltage difference between n and p devices caused by the lesser conduction of the p-devices (the SE-bias resistors “steals” them 25mA) and perhaps a small Vgs difference between n and p. This means that you cannot try to get both (ugs out and follower out) to 0V with an divider across the voltage bias circuit. FE and output stage have to work independently without a dc current way.
I know that it was my statement to use such resistors across the caps, but I have to revoke it - it is nonsense. There should be no need for trimming the follower output abs. and diff. offset.
The independent output stage stay very constant at about -70mV or so and this can be compensated with paralleled resistors across the 10k supply resistors. Now it really looks like a F4 bias circuit with the difference that it is driven by a voltage gain stage instead of a follower stage and the absence of bootstrapping. Also the F4 do not use a thermistor to compensate the Vgs drift.
But the published gain measuring results in my last post should be right, the removed divider was not seen by ac currents.
I agree with your reasoning regarding the DC offset but I'm less sure about your decision to remove the resistors across the bias generator caps. This will mean that the amplifier has only overall AC feedback, i.e. the DC gain of the UGS will be the open loop gain. If there is any inbalance or any DC at the input, this will be magnified by the open loop gain with distinctly undesirable consequences. Even if you block DC with input caps, you are still left with the potential inbalance issue - perfect balance is very hard to achieve. Does this really work OK in practice, with no problems as the circuit warms up?

The F4 is a unity gain design and hence would not have the same issue.

Ian.
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Old 6th August 2008, 06:41 PM   #1688
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The circuit works good, but without the divider it starts again that the absolute offset of the FE outputs are very difficult to trim and the abs. pot behaves very very sensitive. That could not be normal. There has to be something which can handle this and fix the ugs outputs close to 0V absolute.
(Input offset seems to be ok - about 1,4mV max. measured between input cap and 15k input resistor).
Mr. Pass said that the known resistors to the supply rails have the functions to feed current to the voltage reference and load the ugs outputs.
This only loads the output for AC (plus in my case with a resistor to ground for dropping down the open loop gain)
Perhaps a resistor from follower output to its FE output, than there would be a way for DC for the feedback loop....? ...will try that...

Have done a search in the internet for follower stages and got the discussed approach above as a standard. There are amps with tube- or op-amp front ends, which use this bias circuit (only a vref driven by resistors from the supply rails and coupling caps connected together on front end side) for their push-pull mosfet output stages.
Also I found more possibilities to realize the coupling between fe- and ouput-stage.
Perhaps it is possible to build the bias network without coupling caps. Have seen a circuit with only one elcap across the complete voltage reference plus a divider which is driven from the op-amp in its middle. But I think it will not give the 4V more voltage swing and also this would generate back the problem with the divider mentioned in the last post.

I believe I am going in circles................. :-(


Mr. Pass may I ask you directly the following two questions?:
1) What is the dc current running through each jfet and each ugs level shifter?
2) Do the elcaps across the bias circuit in your design decouples the FE from the output stage in the same way as in a F4 with no DC signal path between fe output and follower stage (only the feedback resistor: follower output to diff. pair input)?

Also a question to the experts out there: Can somebody explain why the measured closed loop gain in post 1684 point 4) is only 24,3dB and not 26 or 27dB?


PS: Ian, I only was refering to the voltage bias circuit in the F4 not to the complete amplifier.

Regards
Dirk
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Old 12th August 2008, 11:13 PM   #1689
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Hello,

hope there is any interest in this project – seems that I am the only one who tries it :-(

Here are some new details:

Have changed again some resistors with the result that the absolute and differential offset is very stable now:
I came to the decision to put in again the divider across the voltage reference and throw out the frontend loading resistors to ground – have found out that the divider only has the effect of a shifting ground (the supply voltages starts to become unsymmetric) in combination with this output to ground resistors (but I don’t know why this happened).
Also the trimmers have been scaled down: Abs. pot is now 20R and diff. pot 50R – both are 25 turn types.
I have implemented the resistor from FE to OS which I have also seen in the A75 article. (The A75 uses a combined feedback from output and front end.)
In the shown circuit below the feedback is not mixed and only comes from the OS. But mix mode can be realized when changing the 0R resistor to a higher value.
My main goal was to get a really good trimmable offset and this is done now and works very well - both offsets are adjustable to 1-3mV without a problem (but I can’t say if this resistor has a negative effect and how to dimension it!?) and the supply rails stay symmetrical.
The abs. offsets of the FE reaches values in size of +140 and +180mV - think that is acceptable (perhaps it can be reduced with a bit higher resistor value for the upper divider resistor)
Also new are the four resistors in the bias circuit connected to ground – it could be that they are not necessary - perhaps they bring a bit stabilization.
The two resistors which steal the voltage references some current in stand by mode are reduced to 270k which give a stand by output bias of only 26mA (2mA p-fet + 24mA SE-resistor)! That’s a consumption reduction to a tenth. The abs. offset goes down to -120mV and for diff. offset I get about 12mV.
However I need another possibility to throw away some open loop gain which is still to high.
Without the ugs output to gnd loading resistors the open loop gain raises again by 4dB.

Perhaps other people will try it out or have some ideas!???

Regards
Dirk
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Old 15th October 2008, 08:58 PM   #1690
Jozua is offline Jozua  South Africa
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Hi

I have the Revision 1 Boards. Where could one purchase the latest revision and can I expect a drastic improvement in sound ?

Thx

Jozua
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