F5, strange problem...

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Hi,

I built F5 with 2sk170, 2sj74, Fairchild mosfets.

I used Jims audio board, firstwatt look clones (nice spanned transistors...)

My problem: I was able to bias one channel, run it at 1,3 A, I shut down the power supply. Then I repowered (after 1h), and bias shot up. Luckily limited by the lab suply. Now I can't readjust bias, it shoots up on one polarity. First I set to zero bias, then I was able to bias around 0,4 A, then I cant really do any senseful adjustment...

What is a possible problem? Jfets get quite hot, I really have no idea.

With the other channel, I was in the adjustment process:

All was fine, I touched the input cable, suddenly lab supply shut down voltage(due to current limiter), Pmosfet: G=2V D=10V S=10V, Nmosfet: G-25V D=10V, S=-25V

Sj: D=-25V, G=1,9V, S=1,6V,
Sk: D=2V, G=1,9V, S=1,7V

I could not trim down the voltage, I decided, the sk was dead. removing the sk brought down the bias to zero.

My questions: Any idea?

Further questions: Which gate source voltage is required to make the fets conducting?

Is it possible, I killed the jfets (In the second case, I'm 99% sure, the sk is gone...)

I alwas thought, jfets are not in danger touching them... (the input pin..)

Please advise.

Regs, Dirk
 
Here some pics:

I put the pots to minimum. Current reading was: 30mA neg, 90mA pos.
then 50mA neg, 100mA pos. JFests hot, shut down.
Restart: neg, 10mA, pos 70mA, now stable.

I did some measurements:
Offset around 0,3V
Drain of Jfets: around +-23,9
Gates at 1,1V (How can this happen?)
Source K: 0,5V
Source D: 0,04V

I would expect the Gates at 0V.

When I started the first succesful current adjustment, current was about 20mA, pos and neg. I get the impression, R21, R19 suck 2mA, so talking errors in the Lab supply, there were around 15mA in the Jfets.

I get a lot of bad ideas... Maybe wrong IDSS? But I bought these from EUVL, so it should be fine. What IDSS should be used? (With the resistor values in the schematic?)

Overheating of fets due to to much current??? What confuses me most: One channel worked for 1,5h during adjustment. Then I shutdown, an connecting it again, current shot up.

The second failed during adjustment. It ran half an hour, then I touched the input cable, maybe not even electrically... Current shot up, lab supply decreased rail...

Please help to sort my ideas.
 

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Official Court Jester
Joined 2003
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if you bought them from Patrick , do not bother with measuring Vp (pinch voltage )

just check them for Idss , to check is gray smoke still in them

besides that - triple check all resistor value/position , all solder points , same as proper isolation of mosfets vs. heatsink

during setup procedure , inputs must be grounded , while outputs unloaded

dunno for jimsaudio schematic - is it proper or not

I hope you transposed those to using proper Diyaudio F5 schematic
 
Last edited:
Official Court Jester
Joined 2003
Paid Member
Hi, tomorrow I'll measure idss. But what is vp, how can I measure??? During adjusment, I had the input open: there is 100k agains ground, so there should be ground reference...

I used the original schematic and doublechecked.

google for Jfet pinch voltage - read Papa's articles on FW site , find Borbely JFet papers



when I said inputs grounded , I know what I mean

now is your turn - to figure what I meant

:clown:
 
measurements...

I measured the jfets of the temporarily working chanel.

exemplare k170:

Lab supply 12V, source gate connected, drain +, g-s -, in between fluke in mA setting.

I measure zero current flowing.

So I fried the jfets.
 

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@Zenmod, I got what the pinch off voltage is. Next step: Check pcb again, new jfets.

Shortcut input during adjustment. Do I need a output load?

What IDSS is required for the jfets? Please give a recommendation for the resistors used in the schematic.

Merry christmas.

Regs, Dirk
 
Official Court Jester
Joined 2003
Paid Member
as I already said - shorted input , no load at output

Idss - considering prescribed BL group , that means everything from 6 to 12mA will do the job

it wouldn't hurt if you read few existing tutorials how to ... F5 , search in 6L6's signature for that

recommendation for resistors ...... what you exactly mean with that ?
 
Official Court Jester
Joined 2003
Paid Member
when Idss is on lowish side , there is not enough resistance in drain to result in big enough voltage drop , needed to open output mosfets (say 4V-ish region)

when that's the case , cure is increasing value of resistor(s) in parallel to trimpot(s)

or - even better - paralleling input JFets , which is approx. doubling their Iq , xconductane ,halving (stage) output impedance etc.....
 
So, it took some time longer...

I finally got it running.

Steps I had to perform:

- resolder 3 "not so hot" solder point
- replace 2sj74/2sk170 fets
- put 220uf electrolytics in the powerlines (I use a regulated lab supply)
- clean powerfets and cooler with isopropanol, new kapton isolators
- shortcut input with alu foil and clip

I then limited lap supply current to 2A and started.

Result: No problem adjusting the idle current. Everything as it should.

So, the right channel is working.

Next, I will fix the left channel.

Thanks to all of you for the encouragement.

Regs, Dirk
 
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