Recommendation for 5-10W amp.

Francesco, I can guarantee the sim in # 60 did not incorporate the variation of Vgs threshold due to temperature of the IRF into calculation.
It is quite certain that the ckt will enter fatal thermal failure within a few minutes, even with a gigantic 0.25/K HS.

I understand what you mean, but you have taken into account the following:
  • The low supply voltage
  • The use of a hexfet of moderate power and current and its relative not very low channel resistance.
  • The decrease of voltage drop on the gate of the MOSFET due to the temperature increase?

In any case a larger heatsink only accelerates the rate of destruction of the component.

I have worked with the big uhc-mos such as 2SK1297, 2SK2554, IXFH58N20 and I know with certainty that their vulnerability is directly proportional to the maximum current, so it was necessary to include appropriate source resistors to slow the current. But those are other beasts.

On the other hand, I think the IRF530 will cost around € 2. It will not be a big loss, you do not believe?
 
. . . In any case a larger heatsink only accelerates the rate of destruction of the component. . . .
Hi Francesco,
Could you elaborate more detail on the mechanism leading the aforementioned statement? Kindly share your experience. This is very interesting and important for me and could lead to redesign of some of our equipments. I learned a lot of important tricks on this forum.
My work get me involved with enough IRF 540. On a small heatsink with 6W dissipation at idle, a 540 will be destroyed in about 10 - 15 minutes at 25C ambient solely due to its positive temperature coefficient transconductance nature (Id increases while Vgs threshold decreases with temperature). I think fried enough to note the time. I do not think the 530 will be much stronger.
We consider ourselves more lucky to still be able to get he IRF540 at around € 0.50, about € 2 for the 2 pairs down here, but not exactly what we can call cheap because the average daily income of many of our people is only around € 4.
I can see that the circuit in #56, the decrease of voltage drop on the gate of the MOSFET is due to the reduction of Vbe of Q6 and Q7 due to the temperature increase. But it will not compensate for the increase of Id at the elevated heatsink temperature. It was not mention to mount Q6 and Q7 on the heatsink. Is there other mechanism I need to consider?
:cheers:
 
Hi Francesco,
Could you elaborate more detail on the mechanism leading the aforementioned statement? Kindly share your experience. This is very interesting and important for me and could lead to redesign of some of our equipments.
:cheers:

I am available to describe the experience gained with the vertical mosfet and the uhc-mosfet in particular, because I believe that in a few know what really happens, indeed creating around urban legends.

The first lie is that the drain current of these devices has a positive coefficient. In practice, indeed, the coefficient is negative, similarly to the lateral mosfet.
In Vertical is also negative the coefficient VGSth vs. temp.
The substantial difference between the two types is instead the transconductance (much higher) and the resistivity of the channel (much lower) in the vertical (in particular hexfet and UHC).
These huge two differences with the negative coefficient of the VGS threshold, which generally are the cause that can lead to the destruction of the component. A phenomenon that I remember I have labeled as "silent death".

Well, now we see in detail what happens.
For a practical example, imagine the push-pull output stage of the post 56 and we make an analysis of the dc bias current over the time.
When we give power to the circuit, it will establish a current that will be a function of gate voltage (bias), supply voltage and resistance of the channel under those initial temperature conditions.
The current begins to flow, because of the aforementioned resistance, will cause an increase of temperature of the component which in turn due to the negative coefficient Vgs / temp will increase even more the current in an iterative process. But in the meantime there is another phenomenon that is occurring: the increase in temperature causes an increase in the channel resistance of the same, that will tend to oppose the increase of current caused by the first phenomenon. The condition of maximum current will depend on the aforementioned parameters of the component and from the supply voltage.

If these maximum values ​​of current and power rating are bearable by the device, it will survive, otherwise it will destroy. Assuming that it have reached the critical point without damage, then due to the temperature, that for inertia, will continue to grow, and so also the resistance of the channel, so the output current will tend finally to decrease, until they reach another stable point of definitive equilibrium.
In a chart, Current / time this translates visually into an initial hump.

Now back to the original question of why these components are more susceptible to self-destruction the answer lies in the high value GM / Rch. In particular, the more the resistance is low, the lower will be the thermal effect which causes the increase of resistance of the channel to limit the circulating current.

For this reason:
More devices are large (not as physical dimensions :D), most they are prepared to die for this phenomenon.
More larger heatsinks and the situation is even worse (the temperature of the component will be colder).
The only effect will be a delayed time of the phenomenon.

In these cases, better proceed to a lower supply voltage or towards a small power component (greater channel resistance), or a source resistor proportional to the power device (more power device, more high resistor).
 
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. . . The condition of maximum current will depend on the aforementioned parameters of the component and from the supply voltage. . . .

Very interesting, thank you for the detail explanation. I think the legend spreads due to the fact that many of us have had one silent death too many before, are over cautious and lack of a better explanation.

Let's use #56. Assuming an initial bias of 500 mA and 12V supply, 6W is dissipated on the IRF530. At 25C ambient and a 2 C/W heatsink, I estimate heatsink temperature will stabilize at about higher than 50 C. If we maintain Vgs bias, Drain current will be at around 1A dissipating 12W. From the very rough estimate, seems that failure could be avoidable. Probably even able to survive a 1A initial bias. Kindly correct if I make any mistake.
Moreover, I still have no clue how to take the effect of the thermally induced increasing channel resistance into account.
Do you have a better way to arrive at a more accurate estimation?
 
It's weekend after all Andrew, many would rather enjoy other activities rather than sit in front of a pc, maybe a bit later. It's getting into a less explored area. In this part of the forum, it is second nature using 1A bias or more at 23V and above for vmos, with ACA being an exception. I need to calculate rather carefully to avoid posting misleading opinion, a task many would rather avoid on a nice saturday.
 
Very interesting, thank you for the detail explanation. I think the legend spreads due to the fact that many of us have had one silent death too many before, are over cautious and lack of a better explanation.

Let's use #56. Assuming an initial bias of 500 mA and 12V supply, 6W is dissipated on the IRF530. At 25C ambient and a 2 C/W heatsink, I estimate heatsink temperature will stabilize at about higher than 50 C. If we maintain Vgs bias, Drain current will be at around 1A dissipating 12W. From the very rough estimate, seems that failure could be avoidable. Probably even able to survive a 1A initial bias. Kindly correct if I make any mistake.
Moreover, I still have no clue how to take the effect of the thermally induced increasing channel resistance into account.
Do you have a better way to arrive at a more accurate estimation?


This behavior of uhc-mosfet is difficult to compensate, because at the same time there are more non-linear phenomena. At a minimum, require two different compensation circuits with opposite characteristics. During the first phase of growth of current (positive derivative) should be active a negative compensation circuit, vice versa, during the decreasing phase current, should be in act a positive compensation circuit. In any case these compensation circuits over that delicate in tuning, they considerably complicate the circuit.

That said, let's see if and how we can deal with and survive the initial problem.
We return to our circuit of the post 56 and you imagine that after bringing the circuit at a temperature of approximately stable regime, you adjust the gate bias voltage for 500 mA.
We suppose that the above bias voltage is 4.00 volts. That said, keep in mind that this value is a value obtained with the “hot” circuit (say 50° to make your example). We can also infer that the resistance of the channel was 12000/500 = 24 Ohms.

Now turn off the circuit and rekindle it the next day. The ambient temperature is 25°, so the ns. devices are at this initial room temperature.
We know that the resistance of the channel will now be more low, so applying to the gate the same 4.00 volts, the component appears in upper_bias condition, from this point of view.

In reality it is not so, because the threshold voltage will be increased to this lower temperature and so the output current will be lower. Two overlapping non-linear phenomena with opposite effects.
They will be difficult to resolve.

So, we neglect for a moment the variable Rch and focus our attention on the VGSth variable that is definitely more dangerous. Some datasheets report this value and others do not.
They, however, are valid under certain operating conditions that substantially may be different from our case, so at the end result will not be easily derivable, but we try it.

From the documents in my possession, in the tempco range from 50° to 25° I have derived a variation of Vgsth of 0.2 V. Taking into consideration a maximum value of gm = 8 (precautionary), it would be an increase of 1.6 A with respect to the reference. what a reference? 500 mA? no.

Let us consider now the resistance of the channel in the regime (50°) we have seen to be 24 ohms. At a temperature of 25 ° it results in a decrease of 0.80% = 19 Ohm. So the result current is 630 mA, which, added to 1.6 A, lead to a total maximum value of 2.23 A.
Conservatively, the peak power of the transient phenomenon is therefore 12x2,23 = 26.8 W. In fact it should be lower, because in the meantime the resistance of the channel has increased . The device is expected to survive.

If the room temperature is lower? More risk.

Remember: in these devices the death comes from cold.


Let me know if I made mistakes.
 

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. . . Let us consider now the resistance of the channel in the regime (50°) we have seen to be 24 ohms. At a temperature of 25 ° it results in a decrease of 0.80% = 19 Ohm. . . .

Sorry Francesco, my understanding of mosfet channel resistance is different. There are 2 separate description of channel resitances here.

The first being the measured channel resistance at the operating point, the calculated 24 ohms. Let's call this Rch. On a static bias, Rch is solely dependent upon Vds and Id. However, Id is dependent on Vgsth which in turn dependent on temperature.

The second channel resistance that does rise with temperature according to Fig 4 of the IRF datasheet is called Rds(on) which is the inverse of the slope of the transfer function at linear region of a mosfet. This is measured by varying Id and Vds on a drain loaded mosfet driven deep into saturation.

I do not think it is valid to apply published data on Rds(on) to calculate Rch, so the 19 ohms value can not be used. And I have never seen any Rch behavior vs. temperature published on any mosfet datasheet.

. . . range from 50° to 25° I have derived a variation of Vgsth of 0.2 V. Taking into consideration a maximum value of gm = 8 (precautionary), it would be an increase of 1.6 A . . . .

This way of estimating current is rather inaccurate and going roundabout. I'd prefer opening the IRF datasheet and look at Fig 3. At 25C and 500mA Id, Vgs is about 4.25V. Going straight up at the curve vertically, Id is about 1.6A at 175C. Let's say around 1A at 100C (actually a bit lower) and will be lower if the temperature is lower.
No need to derive any Vgsth variation.

But still I find this method not satisfactorily accurate. I fried enough 540 remember? There are still other factors unaccounted for like device variation. Also the Fig 8 SOA is published only for a single pulse, no clear data on DC operation.

. . . If the room temperature is lower? More risk.
Remember: in these devices the death comes from cold.

I fail to see the supporting logic behind these statement.
Yes, circuit at #56 may survive short term failure but how long would the devices last at 100C? I think it is dangerous to operate devices close to 100C continuously. People may get burned and most electrolytics would not survive for long. And yet, my estimation of the steady state condition is not accurate, it could be running at just 50C with 2C/W HS.
 
Sorry Francesco, my understanding of mosfet channel resistance is different. There are 2 separate description of channel resitances here.

The first being the measured channel resistance at the operating point, the calculated 24 ohms. Let's call this Rch. On a static bias, Rch is solely dependent upon Vds and Id. However, Id is dependent on Vgsth which in turn dependent on temperature.

The second channel resistance that does rise with temperature according to Fig 4 of the IRF datasheet is called Rds(on) which is the inverse of the slope of the transfer function at linear region of a mosfet. This is measured by varying Id and Vds on a drain loaded mosfet driven deep into saturation.

I do not think it is valid to apply published data on Rds(on) to calculate Rch, so the 19 ohms value can not be used. And I have never seen any Rch behavior vs. temperature published on any mosfet datasheet.



This way of estimating current is rather inaccurate and going roundabout. I'd prefer opening the IRF datasheet and look at Fig 3. At 25C and 500mA Id, Vgs is about 4.25V. Going straight up at the curve vertically, Id is about 1.6A at 175C. Let's say around 1A at 100C (actually a bit lower) and will be lower if the temperature is lower.
No need to derive any Vgsth variation.

But still I find this method not satisfactorily accurate. I fried enough 540 remember? There are still other factors unaccounted for like device variation. Also the Fig 8 SOA is published only for a single pulse, no clear data on DC operation.



I fail to see the supporting logic behind these statement.
Yes, circuit at #56 may survive short term failure but how long would the devices last at 100C? I think it is dangerous to operate devices close to 100C continuously. People may get burned and most electrolytics would not survive for long. And yet, my estimation of the steady state condition is not accurate, it could be running at just 50C with 2C/W HS.

What I tried to do, as I mentioned above, is an attempt to relate what I observed experimentally happen to uch mosfets. These results were not in agreement with what one expects from the datasheets of components. In fact, all the parameters would lead in one-way to an increase of the output current in relation to an increase in temperature.
Everything would be so much easier and we would be happy
But if that were so, how logically explain the destruction of the components after 10-20 minutes from the power-on, as you and someone else have said?
For example, if you have adjusted the bias to 1 A at operating temperature, because then the next time you turn on (the next day), the circuit goes up in flames within 20 minutes?
Maybe that mosfet suffer from the "morning-after syndrome"? :D
Okay, many people at this point, insert a beautiful source resistance and the problem is solved. Physically, but not logically.
Now, my approach is certainly not rigorous, but that attempts to reconcile logic with facts.
We would need some expert or a professor, but I doubt of their intervention. These people flinch when they hear it stinks.

having said that, we go to your questions.

You are right on the Rds, but the Rdson is not usable and for the Rch data does not exist, so in the absence of another, I have taken curve of Rds-on as the reference .
Another point: the current.
The graph of Fig. 3 of the IRF is impractical and misleading to our situation. Better to refer to the output characteristic.
You remember when I said above that the gate was in upper-bias situation? I meant to say that the greater pressure of 200 mV voltage would tend eventually to a higher current. of 1, 6 A. Again, this value is not correct because it depends on the value of gm at that point that would surely be lower. But as mentioned this is a rough and prudent calculation.
Regarding the last point, I will tell you my experience, hope you understand what I mean.

I had my amp circuit connected with signal generator and to the load and after having calibrated the bias, I gave signal to bring the output power to 100 watts. As time went on, just checking that everything was under control, maintaining throughout the period the power to a constant value. They spent 2 or 3 hours and everything was ok. Eventually I turned off everything and I went happy to home.
Next day, without changing anything, I turned on the circuit, but strangely after 10-20 minutes transistors went up in smoke. I put in a new pair and run away from zero with the adjustment of the bias. Eventually wore the output signal at the same level of the previous day. This time I keep under control it for 4 or 5 hours continuously. all ok. I thought it as an isolated case.
The following day, I turned on the circuit but also this time, after a bit time the transistor burned again. I was thinking of interference, oscillations and the like, but I could not find anything like this. This story was repeated for several more days, even excluding the signal generator. The mystery deepens. I turned off the circuit and turn on immediately: all okay, then I let it for hours at maximum power: everything ok.
But when I let it off for several hours or until the next day, and then it returned in power on, mosfet go in flame. So I began to think that the problem was in the transient from cold to hot temp.
Thus at the next start up I would keep under control the output current. It was observed that the current grew, starting from a very low value, first slowly, but then in an increasingly accelerated, in a sort of snowball effect.
Please take note that when I made replacement of components , this initial phase was by-passed , since I was forced to start with a very low bias voltages , and then slowly rise until they arrive at the right level of bias. In the meantime, however, the devices were already partially heated and it was for this reason that never broke down even more, also at high power.
Indeed , I noticed a slight decrease in bias current .
Then I inserted resistors of source, of value not exaggerated to not increase the output impedance , but enough to save devices . At that time it was summer and I thought I had finally solved the problem. All continued to work fine, until in the winter the outside temperature is lowered and then the problem reappear .
So, long story short, I had to increase the resistance source to avoid other problems. Clearly, the initial lower temperature (then lower Rch ) in the initial struggle gave as a result the overall benefit to the increase of the current , which, being little braked, sent device into destruction .
So the above sentence I highlighted is to be understood in this sense and not obviously that the devices have to work in high-temperature regime.

I hope now everything is clear.

Best regards.
 
Ok Francesco, a lot clearer now on your statement "death comes from cold". Your sharing helps expand my understanding of hexfets. We have a failure mode due to initial temperature condition. Could be due to a slow or uneven heat propagation on rapid rise of temperature leading to hotspot formation or thermal runaway below a critical low initial temperature. No wonder my frustrating failures on attempts to find safe DC operating point.

I believe your need to add a bit more explanation the statement because it can also mean the mosfet will die if temperature is kept low like forced cooling or operating the device on low dissipation condition. That implication can get you misunderstood.

Going back to #56, could you repost the expected voltages and currents that was deleted for reference. I got confused because my calculation shows that the circuit will not function because the maximum Vgs bias can only be set to about 2.5V, which is still below the 3V Vgsth.
And I would also be very interested on your method to make sure that the circuit is unconditionally safe without source degeneration.
 
Hi,

Can we please get back on topic. What I'm looking for is a simple but good sounding amp that' powered via a single rail 24V power supply, clean 5W class A amp using Laterals at the output, different sounding than ACA.

Well, JUMA provided me with a excellent schematic on post 30 that I will be building very shortly. Thanks Juma.

Other post showing 3 stage amp does not sound good to MY ears. For me the KISS principle is king in Audio.

If you have any recommendation please feel free to share them. Even a 3W amp would be sufficient for my needs, a low power Hiraga (2-3W) would be fun to work with but no schematics with recent components seems available on the web. I would of course not discuss an Hiraga design on the Pass forum.

BR,
Eric
 
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Probably like you Eric, I also prefer Lateral mosfets for output device. However here, in Pass section, vertical mosfet is the norm. We learned to use thermal compensation and source degeneration resistor for thermal stability. But Mos57 "controversial" circuit use none.

To me, this less traveled territory is interesting because it may open the door to a simpler mini F5 topology free of both thermal compensation and source degeneration. I was just trying to determine the boundary. Most likely is that your requirements of 24 V (or +12V and -12V) and 5-10 watts lie within the safe zone.

If a safe boundary condition is found, you can replace the laterals on Juma's circuit with IRFs with minor R3 and R5 adjustment for a different sonic experience.
 
Seconds me? Please clarify.
I calculate Vgs on #8 to be about 1.1V and Id at less than 0.4A, for a latfet with with 0.15V Vgsth. Juma modified R3 & R5 to 1K to give 0.7A Id at #30. Any particular point you want to make? I am ordering parts to try your circuit. It truly is interesting, but I don't think I can use the 540N and 9540N that I have. It's all right if you are reluctant to repost. We went OT for too long allready.
 
PLH low power version...for high efficiency spkr.

How about the PLH design but instaed of using a single rail 40Vdc supply it would be powered by a 24-27Vdc supply just like the JLH was originally designed to work with.

Not exactly sure what would need to be modified from the PLH to make a lower power output version but I would certainly be willing to give it a try if someone would help me figure this one out.

Thanks,
Eric
 
How about the PLH design but instaed of using a single rail 40Vdc supply it would be powered by a 24-27Vdc supply just like the JLH was originally designed to work with.

Not exactly sure what would need to be modified from the PLH to make a lower power output version but I would certainly be willing to give it a try if someone would help me figure this one out.

Thanks,
Eric

Good choice
 
I'm sorry, I did not realize that it had been resubmitted in post 30.
In it appears that the Vgs voltage is 1.4 V.

Now, allow me to defend my "controversial" circuit .
In particular, I want to explain why I replaced the latfet with hexfet . As I mentioned, it was a necessary choice to improve the overall performance, in particular the spectrum of harmonic distortion .

The motivation is precisely due to the low value of the Vgs voltage for latfet.
This last is also the Po point work of the input transistors . So, in case of latfet , this point is almost at the edge of the load line of BJT , in an area just at the limit of linearity and class B.
With the employ of Hexfet that requires 4 or more volts for the same output current , the input transistors work in a more central area , so more linear and moreover, in class A.
In addition, in my opinion, it makes more sense that out stage work in class A when it is driven by another class A stage, but much less sense if it is instead driven by a class B or AB . I enclose the drawings of the load line and the working point in the two situations . Imagine superimpose them the output characteristics of the transistor and the result is under your eyes. :cool:
 

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