Strange behaviour of my F5 - diyAudio
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Old 5th May 2013, 09:04 AM   #1
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Default Strange behaviour of my F5

I had made F5 boards a couple of years ago but never followed up this project. Until today, when I mounted them onto heatsinks and fired them up.

Strange thing. Increasing the resistance of the pot in the positive half of the circuit does not result in any bias setting. The same procedure at the negative half enables to set the bias on both halves and now allows to trim the positive side too.

It is not possible to bring the offset down to 0 V yet. At a bias setting of 1.3A on both halves (~600mV voltage drop over the Source resistors) the voltage drop over the JFETs' Drain resistors is ~4.3V (negative side) and ~5.7V (posistive side). The offset voltage is ~-130mV.

The second channel shows the same behaviour, but the difference between the positive and the negative half is even worse (>300mV offset voltage).

The JFETs of both channels are closely matched and I cannot see any layout or stuffing errors. Need consolation and advice

Last edited by permaneder; 5th May 2013 at 09:28 AM.
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Old 5th May 2013, 09:26 AM   #2
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The amp boards include capacitance multipliers and regulate the supply voltages down to ~+-22V
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Old 5th May 2013, 09:33 AM   #3
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measure one side's Rs ( to determine Iq ) and output offset ; who cares what's with other side , as long all values are in 10% bracket

if you can't achieve desired Iq and low offset , increase input Jfet's drain resistors for , say , 25% , then you'll have enough margin for precise fiddling

prior to powering up after that change , go back with trimpots , then repeat biasing procedure

culprit is input Jfet's Ids , they're most probably on lowish side
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Old 5th May 2013, 09:53 AM   #4
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Quote:
Originally Posted by Zen Mod View Post
measure one side's Rs ( to determine Iq ) and output offset ; who cares what's with other side , as long all values are in 10% bracket

if you can't achieve desired Iq and low offset , increase input Jfet's drain resistors for , say , 25% , then you'll have enough margin for precise fiddling

prior to powering up after that change , go back with trimpots , then repeat biasing procedure

culprit is input Jfet's Ids , they're most probably on lowish side

Thanks for your assistance. But I don't believe that the problem is with the JFETs. Their IDSS is >8mA as far as I remember.

I can easily adjust the bias on both halves to 1.3A or more. The voltage drop over the input drain resistors is completely different (4.3V versa 5.7V) however. And the offset can't be set to 0V.

Last edited by permaneder; 5th May 2013 at 09:57 AM.
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Old 5th May 2013, 10:37 AM   #5
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Ugs for N and P mosfets is different , that's the nature of the beast

what you're doing is observing girl's mother , instead of girl itself

just do what I wrote
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Old 5th May 2013, 10:45 AM   #6
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Ugs for N and P mosfets is different , that's the nature of the beast

what you're doing is observing girl's mother , instead of girl itself

just do what I wrote

Observing girls is always better

I'll increase the Drain resistors and will see what happens...
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Old 5th May 2013, 12:30 PM   #7
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I replaced the 2.2k resistors by 3.0k in one channel. There is no change in a positve sense. The pot trimmings on either the positive or negative side correlate closely. I.e., the variation of the resistance of the positive pot influences both sides and vice versa.

The offset is now ~.45V instead of ~.13V.

The difference of the voltage drops over the JFETs' drain resistors is even higher than before.

Last edited by permaneder; 5th May 2013 at 12:33 PM.
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Old 5th May 2013, 01:07 PM   #8
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what you're trying to achieve - symmetry between each element/value/measurement point , or simply - desired Iq and minimal offset ?

as I wrote - measure voltage ( Iq) across one output Rs and offset ; that's all what you need to observe while setting F5 for operation

when you get what's needed ( around 1A6 and ~0mV) , just check voltage across other Rs ; if you're in 10% , that's it - it covers Rs tolerance , same as measuring tolerance

difference between lower and upper mosfet's Ugs is of no relevance , except in case that you're having some serious problems during setup procedure

sorry if I misunderstood , in case you're having some other problems
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Old 5th May 2013, 02:10 PM   #9
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Thank you. Will go on later next week. Now I've to start cooking. My children will come tonight.
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Old 5th May 2013, 03:18 PM   #10
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Quote:
Originally Posted by permaneder View Post
....My children will come tonight.
those are most desirable "problems"

enjoy !
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