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Old 7th March 2013, 08:10 AM   #41
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Default VFET output stage configurations

This seems to work OK with Michael's models. Gives you a nice bias current, all seems to be in accordance with Michael's plotted curves also (more or less at least).
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Old 19th December 2014, 03:27 PM   #42
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Does anyone have an idea of the capacitance values of CDS, CGD & CGS for the 2SJ28 & 2SK82 as all spice models I can find have 0 in these fields.

I've had no luck in finding a full Data sheet...

Any help would be much appreciated...
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Old 20th December 2014, 06:36 PM   #43
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I don't have a full datasheet either, but I can give you some ballpark
information.

Operating the SITs in CS mode and comparing gain vs frequency at different
source impedances, I get an apparent input capacitance of about 1.4 nF
for the SIT-1's and something on the order of 2.5 nF on the 2SK82's. This
seems to be pretty proportional to the chip size / dissipation ratings.

This capacitance would be the sum of Ciss and Crss. When you factor in
the gain in CS mode for different parts and compare, you see that parts
such as the SIT-1, 2SK77B, 2SK92, and the IRFP240 mosfet all end up in
approximately the same ballpark, with the SITs having somewhat less
capacitance.

For thumbnail calculation, you could take the 1300 pf Ciss and 93 pF Crss
of the IRFP240 (150 watt chip) and scale it by wattage. I don't think you
would be far off.

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Old 21st December 2014, 05:21 AM   #44
JohnW is offline JohnW  Czech Republic
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Thank you for your reply.

I'm an old school Lightbox and Track & tape guy so am basically self taught when it comes to the world of computer simulations.

I’m not even sure under what operating conditions the capacitances should be measured, and considering that CDS & CGD are non-linear capacitances and are very much dependent on the Junction voltage – I’m left presuming that the JFET junction should be biased off as with an enhancement mode devices?

With Enhancement mode MOSFET devices the capacitances are normally described:-

Ciss (input capacitance, Drain and Source terminal shorted)

Coss (output capacitance, Gate and Source shorted)

Crss (reverse transfer capacitance, Gate and Source shorted)

So one would presume that we need to bias the JFET device so that its “Switched off” but then how to measure these capacitances with an applied Bias voltage – not with my cheap capacitance meter

Ciss = CGD + CGD
Coss = CGD + CDS
Crss = CGD

I found the first page of the 2SK60 datasheet that claims a Ciss of 190pF, so crudely doubling up the capacitance for the double die 2SK82* gives a Ciss of 280pF – if I only knew the value of Crss then I could simply calculate the others. I am somewhat surprised that for such a power device Ciss is so low… This makes me wonder if its been measured in error as an Enhancement device with an VGS of 0V... (I could believe a Ciss of 1900pF for the 2SK60 which would be closer to your 2500pF for the 2SK82).

*I suspect that the input capacitance of the 2SK82 will be slightly less then twice the 2SK60 as its higher voltage device which will result in a lower Crss…

The poor resolution scan of the 2SK60 datasheet appears to state:-

VDS = -15V & VDS=0V

So I’m guessing it should say VGS = -15V and VDS = 0V.

I have many questions and with so little understanding, I’d like to have a Spice Model of the 2SK82 & 2SJ28 that has values other then zero in these fields – I don’t understand the point of a Spice model with zero for these rather critical device characteristics…
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Old 21st December 2014, 07:44 AM   #45
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Sorry I wanted to correct:-

Ciss = CGS + CGD
Coss = CGD + CDS
Crss = CGD
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Old 21st December 2014, 01:11 PM   #46
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Quote:
Originally Posted by JohnW View Post
I don’t understand the point of a Spice model with zero for these rather critical device characteristics…
Right, I should have cursed the darkness, instead.



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Old 21st December 2014, 01:26 PM   #47
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Old 21st December 2014, 01:41 PM   #48
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Michael,

Please forgive me, my post was not meant as a criticism of your efforts as in fact I've used your models in my simulations and these have helped be greatly with the driver circuit operation - however without the junction capacitances the models are "useless" in determining the amplifiers open and thus closed loop characteristics - this is what I meant to say. Please forgive me for my poor choice of English - I'll never be one for the diplomatic core...

I've struggled today to characterise the VFET's using a leader LCR745G (LCR only upto 1KHz, but with external bias).

What is totally evident (and to be expected) is that both Vgs & Vds has a massive impact on the Junction capacitances - the device behaving like a varcap diode

My current Spice properties for the 2SK82

*PROPERTIES,10
CDS=42p
CGD=142p
CGS=319p
K=0.157
MU=7.3
N=2.24
POL=1
RG=2MEG
VCT=0.0
X=1.51

These are based upon my crude measurements (which I have no faith in, as I don't understand at which "Bias" voltage the junction capacitances should be measured for a JFET device - What I'm trying to say is at what operating voltage does Spice "expect" the capacitance Variables CDS, CGD & CGS to be measured on a real device?

I measured (2SK82 KE-33):-

Ciss 461pf (-15V VGS, VDS 0V)
Coss 184pF (-9V VGS, VDS 0V)
Crss 142pF (-9V VGS, VDS 15V)

I used a 9V battery for the "floating" biasing arrangement.

I stress, please don't take these values as correct, I'm still in the process of trying to understand how to correctly measure these devices.

Today I ordered a HP4275A LCR with option 001 internal Bias, to replace the rather Mickey Mouse Leader - but this will not help much until have have a better understanding of what I'm doing.
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Old 21st December 2014, 01:48 PM   #49
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In our world of Enhancement MOSFETs, there's very little about characterising JFets...

Are the D/S truly symmetrical on the 2SK82 / 2SJ28 ?
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Old 21st December 2014, 01:57 PM   #50
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Also, when looking at the Spice models, with my very limited knowledge of such matters I don't see how the non linear junction capacitances are realistically modelled... measurement with the LCR and external bias voltage demonstrate highly non linear capacitances which if not modelled correctly I cannot see Spice results being realistic?

I presume I'm missing the bigger picture?
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