SIT Startup Problems - What did I miss?

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Hi Dan,

we are mostly used to the capacitor free outputs and check the offset.....

I was in the last days also in the situation to be in panic with the F3 clone and my newly implemented 15 x 1000uF Silmic ... it is easy to forget what ilimzn wrote...

especially when building a new project.....! :):)


but what was the reason your SIT was blown?

:) do you have some improvement with tons of parallel caps instead of one of 15000uf with 15uf MKP decoupling?
 
:) bonne année too.. for the output coupling or source resistor bypass i have very sweet sound with mundorf M-lytic AG and 10uf clarity cap decoupling , sounds better than Epcos skiorel or evox rifa :)

i have heard than the more parrallel caps the less ESR but increase insertion loss ( angle de pertes in french)..
 
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After a couple of little bumps in the road my SIT is up and running. Still needs a little cleanup and more paint but should have some listening impressions soon.

Regards,
Dan

SITDone_zps1874d294.jpg
 
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