lhquam has already matched the output JFETs to within 2.89% versus its original 13.9% which he called a poor performing channel. He clearly concludes to have converged on the sweet spot for Teaser-6. The new mismatch in transconductance [2.89%] still caused a DC offset at the output. This offset is a valuable number. It mirrors the intrinsic mismatch in the Gms of the JFETs. Its value is an objective guide to the extent of mismatch. Measure this DC output offset as a functon of Idss at a fixed frequency. Tweaking the bias pots to zero the output offset does not induce a new magical match between the JFETs. Au contraire, it creates a new mismatch by forcing the Idss of one JFET to track the other where it shouldn't. IMHO, one needs to adjust the bias pots of both JFETs to get one identical value of bias voltage. Allow the DC output offset to settle where it naturally has to due to the intrinsic mismatch of the JFETs. Use an output capacitor to block DC , and carry on.
With the transformer coupling, I cannot see any reason that the absolute level of the FET bias voltage Vgs matters at all. The transconductance is important in determining the relative modulation levels of the two output FETs, and thus H2.
The G-S Threshold voltage of each device also plays a role in the "intrinsic mismatch" of the circuit (offset).
Au contraire
I can undestand your use of "Idss" but, to assciate it with frequency? It more than likely adjusts the output offset and matches Id, causing a very slight mismatch in the Bias Voltage of the 2 deivecs. The Vgsth voltage will likely not be equal and this will be necessary for 0 output offset. These are DC conditions.AC wise the Vgsth and Id mismatch, even after offset adjustment, will likely have much less effect on distortion than the gain variations due to tranconductance mismatch IMHO
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Can someone point me to some original discussion or schematic for the "Zen amount pot"? The only schematic I have found is this: http://www.diyaudio.com/forums/pass-labs/201655-lamp-simple-sit-amp-62.html#post2891896
That it. You know the theory. It is simply about your taste and harmonic distribution. Have you tried it with F5T balanced yet? P3 is basically same thing, but control/alteration is coming from FE.
lhquam and flg. Clearly you know your stuff; but unfortunately the 'sweet spot' continues to be elusive; although within the near grasp of lhquam per his matching JFET study. ZM showed a picture of the SIT-1 amp with a meter [for Idss?] on the front panel. Is the sweet spot related to a certain idle Idss of the output stage? My thinking in my previous post was as follows by this example: If the upper JFET has a Gm = 8.0 S, then a Vgs = 1.0 Volt enables an idle Idss = 8.0 A to flow through it. By comparison, the lower JFET has a Gm = 7.0 S. So the same matching Vgs = 1.0 V as for the upper JFET, generates an idle Idss = 7.0 A to flow through it. The two JFETs are connected in series, and thus must pass either 7 or 8 A; otherwise create a voltage divider [DC offset]. So, the DIYer tweaks the bias pot of the upper JFET down and/or the bias pot up of the lower JFET to get either 7 or 8 A and zero output DC offset. Except, the range of Idss [of 7-8 A] is where the sweet spot resides; but at which tweakable steady state of idle Idss. Will it be at 7.1 A which is closer to the Gm of bottom JFET or by contrast at 7.9 A. Thus, one has 10 incremental steps = 0.1A Idss [or more or less] to tweak [with the same bias pots] so as to nail this sweet spot down. Except; an attendant output DC offset must develop with each tweak. Can't have your B-day cake and eat it too [your guests took care of it]. Flow with [aka tolerate] this offset to find the sweet spot.lhquam, I was slower at the keyboard but, I beleive I agree
DC offset must remain in safe boundaries , while varying THD content
already shown how to in this very thread
anyway - different constructions , different ways for varying Amount of Zen ...., but none of them is allowed to alter DC offset
lhquam's search for an answer in the Zen Pot of the SIT amp is an interesting development. Clearly, the issue of device matching is irrlevant vis a vis SIT; a solo performer. Is the Zen Pot tweaking Idss and Vds of the SIT? If the answer is yes, then this tweak is moving or shifting or off-setting Vds [new status] from its parent value before the tweak as one hunted for the sweet Idss point. Uh Oh.. I am saying exactly what you said all along. SIT has a DC output blocking cap, and thus one will easily ignore a +/- 1 Volt shift in its Vds. It is irrelevant to its DC offset; it has none. But a similar DC output shift in offset for F6 clone is not tolerated, and is clearly managed with a blocking cap once its sweet Idss is found.
speaking strictly about F6 and MR's amp - with pot you're varying degree of either direct AC modulation , or AC degeneration (indirectly influencing AC modulation)
in both cases it's strictly area of AC , while biasing/DC offset is strictly related to static, DC area
so , how's that suddenly connected with DC offset ?
in both cases it's strictly area of AC , while biasing/DC offset is strictly related to static, DC area
so , how's that suddenly connected with DC offset ?
obviously neither you nor I , have enough mileage or knowledge to understand how young or less young Pass was/is thinking ......
sometimes I see something twisty/funny in his schematics , but that's only making me happier , not really smarter ....... but that's not his fault , but mine
Poetic and wise words. Are the potentiometers in the schematic [L'Amp; A simple SIT Amp] independent or ganged/track?obviously neither you nor I , have enough mileage or knowledge to understand how young or less young Pass was/is thinking ......
sometimes I see something twisty/funny in his schematics , but that's only making me happier , not really smarter ....... but that's not his fault , but mine
The accidental and equal settings of 60% on both of the 10 K pots gave the impresion they were ganged. You are correct. The 10 K pots are independent. One 10 K controls bias [to -10V], the second 10 K which is hooked to the 47 uF cap is the Zen Pot.I thought we had this figured out
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