F6 Amplifier

Antionel,
I could be totally wrong, but I was considering this if both fets are seeing the same signal.

KAsey,
What is preventing DC through the coils? Doesnt the coil see the DC bias for the fet or is your cap stopping that?

There is no DC through the coils because the insides of the fet looks like a blocking capacitor between the gate and the source (simplification i know) therefore no dc current can flow.

Regarding the capacitor in my diag, that was there just to stop oscillation risk with the hitachi 2sk parts. It doesn't do any DC blocking. Also, I found that it wasn't needed with the semisouth R100s.
 
Correction to the Frequency Sweep plot in post #890. A software bug was causing the weird behaviour at low frequencies.
 

Attachments

  • F6a-fsweep1.jpg
    F6a-fsweep1.jpg
    112.5 KB · Views: 473
You shouldn't need those caps.
The main problem with this circuit is that it is sensitive to rail voltages. If the fluctuate, the bias changes. There will be only a couple of microamps through the coils due to the FET gate leakage. Otherwise there is no DC path. My R100s have Vgs=1.33V at 1.3A.

Ah ok I understand. Thank you for the patient explanation - much appreciated.
 
ZM has dropped enough hints that much of the solution F6 design can be deduced. There have been many detours and blind alleys in this thread, but one or more solutions are near.

Since Nelson has not given any detailed performance data, I cannot judge how my "simple design" compares, but I suspect it is close.
 
What detailed performance data are you looking to compare?

:cool:
How about the frequency sweep in post 902, and the other plots in post 890? 1 watt into 8 ohms 1.3A bias on SS R100s. JT-123-FTPCH tx.

The bias in my build is rock-solid. The positive tempco in those SIC JFETs is really nice.

BTW: Looking at the Jensen JT-123-FTPCH documentation, the THD vs frequency behaviour seems to track well. It suggests that my input driver stage needs a lower impedance. I need to try matched K170/J74s in parallel.
 
Last edited:
If drawn with the PSU, don't we see that both fets are passing signals through the PSU to the load, sort of like a circlotron. That is why Kasey got double the gain of what a single fet would yield

That is a nice way of saying it, though nobody told that story about the BA1 ;)
Of course the FET opens up a current capability I independent of the load, hence the output impedance is high and in a load R it will by itself just do I x R = V. And in Kasys example and the full F6, this is V=2IxR of course.

  • About a pentode we often say it is a voltage amplifier.
  • Vout does not track the Vin at all (V is transconducted mystically by Gm to I). And because of the high output impedance of the FET, like a pentode, I like to still call it a voltage amplifier (stupid me, I am dancing on the point of a needle I'm afraid).

IMHO it is the smart feedback that Papa devised for the F6 (and that is different from other similar schema's I have seen) that brings this pentode or typical FET behavior back to normal. I'll be up to it I hope in a few months.
 
Official Court Jester
Joined 2003
Paid Member
I'm on the Mountain now , without special need for M6-ing :clown:

anyway ,few lines :

-no need for astronomic current through bias voltage divider ; 1-5mA is all you need
-feed lower one from +PSU leg , less work for cap across reference part of divider
-load secondary with at least 47K (not much less, please) ; in case of using bias pathh through secondary (one side seeing just gate ) , put that resistor across coil
-as my man Buzz wrote -upper biasing circ of BA1 is having all you need to know -impedances etc.
with or without zener , your choice

hasta la vista Baby ..... Pa is around

:rofl:
 
Last edited:
Antionel,
I could be totally wrong, but I was considering this if both fets are seeing the same signal.
buzzforb; Unfortunately,the schematic you show attendant to this quote [post#895] will not cut it. The two signals at the output port are simultaneously out of phase and equal in amplitude. They will cancel out each other completely to give a zero output voltage, and thus silence. I believe Mr. Pass has already resolved the question regarding the phase at the secondaries of the transformer. They need to be out of phase which is opposite to that you show.
 
Merci Monsieur.

I believe PP is [push pull] and IST [InterStage Transformer]. Thus, you mean that the upper JFET in Conceptual F6 is pushing current through the load to ground, and the lower JFET is pulling current from ground through the load during one input sine voltage cycle.

I was actually thinking of a topology exactly like Conceptual F6 with vacuum tubes but without an output transformer, and no output coupling capacitor like in a Futterman amp.
 
buzzforb; Unfortunately,the schematic you show attendant to this quote [post#895] will not cut it. The two signals at the output port are simultaneously out of phase and equal in amplitude. They will cancel out each other completely to give a zero output voltage, and thus silence. I believe Mr. Pass has already resolved the question regarding the phase at the secondaries of the transformer. They need to be out of phase which is opposite to that you show.

You sure?
 
triode_al: your call name is partly triode, and you mention pentode above. Can one implement Conceptual F6 [in part or full] with vacuum tubes?

Very easy I think to do:
  • you can do it partly and retain the source follower of the input. The advantage of the Power (J)FET is the low drive voltage; a tube needs much more drive voltage. You might be able to use a Lundahl LL1674 (1:4). Try something like that.

The output tubes then run in OLT style (or SEPP/circlotron style as some like it :)).